tangxifan
|
2c46da6888
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clean-up warnings Verilog routing generator
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2019-05-24 16:29:17 -06:00 |
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tangxifan
|
27b996337a
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fixed a critical bug in Compact Verilog generation for SB/CBs
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2019-05-24 16:14:46 -06:00 |
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tangxifan
|
1ade1f1d3f
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update SDC generator disabled_unused_mux by using RRSwitchBlock
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2019-05-24 15:42:00 -06:00 |
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tangxifan
|
f27b88db8d
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Use RRChan in SDC generator to replace old data structures
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2019-05-24 15:34:56 -06:00 |
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tangxifan
|
27c234711e
|
clean up warnings in SDC pb_type generator
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2019-05-24 15:23:38 -06:00 |
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tangxifan
|
924136e7a2
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Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info
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2019-05-24 15:10:08 -06:00 |
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tangxifan
|
994b90ae53
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updated report_timing for using RRSwitchBlock
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2019-05-24 14:25:51 -06:00 |
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tangxifan
|
eef1312325
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updated bitstream to use new RRSwitchBlock as well as the report timing engine
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2019-05-24 12:54:10 -06:00 |
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tangxifan
|
8f4f590ff9
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update Verilog compact_netlist outputter with RRSwitchBlock classes
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2019-05-23 21:52:12 -06:00 |
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tangxifan
|
ea8c36ce6e
|
upgrade Verilog SB generator using the RRSwitchBlock
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2019-05-23 17:37:39 -06:00 |
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tangxifan
|
4aab93b729
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update class rr_switch_block and be ready for updating the downstream verilog generator
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2019-05-22 22:04:31 -06:00 |
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tangxifan
|
efbc454cdd
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Add Class for RRSwtichBlock and plug-in to replace the old t_sb
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2019-05-22 12:34:06 -06:00 |
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tangxifan
|
ec3b4c86c4
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update file organization and be ready for SB/CB class
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2019-05-21 12:15:38 -06:00 |
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tangxifan
|
8186d6dd11
|
reorganize files and clean some warnings
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2019-05-21 10:17:54 -06:00 |
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tangxifan
|
b185a17359
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add routing_channel unique module generation
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2019-05-20 22:33:17 -06:00 |
giacomin
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ceee28226e
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-20 16:47:07 -06:00 |
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giacomin
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8b520349e7
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fixed a bug for rram based fpga when using explicit verilog port mapping
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2019-05-20 16:44:47 -06:00 |
AurelienUoU
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99beeb48cc
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-13 16:42:27 -06:00 |
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AurelienUoU
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a3656dde45
|
Add missing Verilog source, Archictecture folder and Testbenches correction
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2019-05-13 16:41:35 -06:00 |
Baudouin Chauviere
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b48a27acf0
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-13 14:45:57 -06:00 |
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Baudouin Chauviere
|
2019840d7c
|
cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
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tangxifan
|
3313eac23b
|
add rr_chan obj
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2019-05-10 22:50:08 -06:00 |
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AurelienUoU
|
9c05a4fb0a
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-10 14:09:23 -06:00 |
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AurelienUoU
|
ff9b84d800
|
Bug fix in Icarus requirement
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2019-05-10 14:07:32 -06:00 |
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tangxifan
|
be4643b8a6
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updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated
|
2019-05-10 10:21:06 -06:00 |
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tangxifan
|
5c646f5de7
|
fix bugs in routing identification
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2019-05-09 21:40:06 -06:00 |
|
tangxifan
|
a9df922412
|
finish the identification on mirror switch and connection blocks
Verilog generator to be updated
|
2019-05-09 21:31:39 -06:00 |
|
tangxifan
|
a3c3f2b892
|
developing compact routing hierarchy
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2019-05-08 20:49:21 -06:00 |
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tangxifan
|
4c6639218e
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-08 14:30:33 -06:00 |
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tangxifan
|
e305e60ee4
|
minor fix on the shell interface of VPR
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2019-05-08 14:29:58 -06:00 |
|
Baudouin Chauviere
|
4f386de2ef
|
gen_xxx functions create mem-leaks because the mem is dynamically allocated inside and not freed. TBD later everywhere
|
2019-05-06 17:25:29 -06:00 |
|
Baudouin Chauviere
|
3b62f8e024
|
Conversion from s to ns for the loop breaking delays
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2019-05-06 16:12:30 -06:00 |
|
Baudouin Chauviere
|
a5a1a376ab
|
Modified code for cleaner delay naming convention
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2019-05-06 12:52:49 -06:00 |
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tangxifan
|
4e3487b691
|
Add latest abc and update ace dependence
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2019-05-03 18:56:03 -06:00 |
|
Baudouin Chauviere
|
7860042276
|
added before after loop breaker constraining
|
2019-05-03 14:00:06 -06:00 |
|
Baudouin Chauviere
|
4e330ee463
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-03 10:43:22 -06:00 |
|
Baudouin Chauviere
|
921b694400
|
Bug fix sdc breaking loop of edges outside current interconnect
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2019-05-03 10:42:35 -06:00 |
|
AurelienUoU
|
42f20eda60
|
Add the user matching for internal register in formal verification script generation
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2019-05-03 10:24:02 -06:00 |
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tangxifan
|
974af5a2ae
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-04-30 14:30:38 -06:00 |
|
tangxifan
|
42daadee2f
|
critical bug fixing
|
2019-04-30 14:30:17 -06:00 |
|
Baudouin Chauviere
|
1ab4688339
|
Create no segment constraint in loop_breaker if none is given by user
|
2019-04-30 12:30:07 -06:00 |
|
tangxifan
|
c46c0fc97d
|
bug fixing for SDC generator
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2019-04-26 14:07:44 -06:00 |
|
tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |