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OpenFPGA
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2241 Commits

Author SHA1 Message Date
Laboratory for Nano Integrated Systems (LNIS) 618c7d44c5
Merge pull request #53 from LNIS-Projects/dev 
Porting Dev branch to master
 2020-06-11 20:06:58 -06:00
tangxifan aaa52b6e89 start using multiple jobs in travis CI 2020-06-11 19:31:38 -06:00
tangxifan 60dd37e086 remove simulation settings from openfpga arch XML 
update travis to split CI tests

fix errors in travis configuration

fixing travis errors in scripts

keep fixing travis

fix travis on build.sh

bug fixing in travis CI

bug fix in travis regression test run

fixing bugs in the travis scripts

bug fix in travis script: remove common.sh in regression test call

keep bug fixing in travis
 2020-06-11 19:31:17 -06:00
tangxifan 58807bfcb3 remove simulation settings from openfpga arch data structure 2020-06-11 19:31:16 -06:00
tangxifan 068d9943e7 update all the templates and regression test cases with simulation settings 2020-06-11 19:31:16 -06:00
tangxifan 1842bf51e1 deploy read_openfpga_simulation_setting in CI on a single test case 2020-06-11 19:31:16 -06:00
tangxifan 1a006f2ddb update documentation for separated XML files 2020-06-11 19:31:16 -06:00
tangxifan f26550141f add missing files 2020-06-11 19:31:16 -06:00
tangxifan dfdfea2081 fix the bug in CMake Script due to splitted simulation setting files 2020-06-11 19:31:15 -06:00
tangxifan cb09896f23 add example simulation setting for openfpga flow 2020-06-11 19:31:15 -06:00
tangxifan 96b58dfdbb use new simulation setting command in openfpga shell 2020-06-11 19:31:15 -06:00
tangxifan 4a2f6dfae2 add read/write simulation setting commands to openfpga shell 2020-06-11 19:31:15 -06:00
tangxifan 15f087598c split simulation settings to a separated XML file 2020-06-11 19:31:15 -06:00
tangxifan b8bc74cc26 trying to fix the dependency problem of VPR GUI in openfpga shell 2020-06-11 19:31:15 -06:00
tangxifan c87dbc4880 start using counter benchmark in regression tests 2020-06-11 19:31:15 -06:00
tangxifan f73dfa2bcc bug fixed in k6_n10_40 architecture 2020-06-11 19:31:15 -06:00
tangxifan 0b9971cb5c try to deploy the memory bank protocol test case to CI 2020-06-11 19:31:14 -06:00
tangxifan 3c10af7f2b bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm 2020-06-11 19:31:14 -06:00
tangxifan baa2c6b7ef update arch to support reset signal for SRAm 2020-06-11 19:31:14 -06:00
tangxifan 8267dad8ef add decoder support for Z signals 2020-06-11 19:31:14 -06:00
tangxifan aac2e8c805 update openfpga architecture for memory bank usage 2020-06-11 19:31:14 -06:00
tangxifan 82b04ae3f0 add SRAM verilog for memory bank usage 2020-06-11 19:31:14 -06:00
tangxifan 5368485bd6 keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level 2020-06-11 19:31:14 -06:00
tangxifan c85ccceac7 try bug fixing in memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan b191732d32 show vvp version in CI 2020-06-11 19:31:14 -06:00
tangxifan dda6fe19ae show iverilog version in CI 2020-06-11 19:31:14 -06:00
tangxifan b9dd47d465 update documentation about memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan e46651e0c1 deploy preconfig regression test for memory bank to CI 2020-06-11 19:31:14 -06:00
tangxifan 3f9afea3e8 add preconfig testbench test case for memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan 03e56f5ca6 deploy memory bank regression tests to CI 2020-06-11 19:31:14 -06:00
tangxifan 288294c23a add fast configuration test case for memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan 73d4c835b7 add regression test case for memory bank 2020-06-11 19:31:13 -06:00
tangxifan 0bee70bee6 finish memory bank configuration protocol support. 2020-06-11 19:31:13 -06:00
tangxifan a1ec6833c2 add memory bank example arch xml 2020-06-11 19:31:13 -06:00
tangxifan e14c39e14c update Verilog full testbench generation to support memory bank configuration protocol 2020-06-11 19:31:13 -06:00
tangxifan 51e1559352 add fabric bitstream support for memory bank configuration protocol 2020-06-11 19:31:13 -06:00
tangxifan 0e16ee1030 add configuration bus nets for memory bank decoders at top module 2020-06-11 19:31:13 -06:00
tangxifan fa8dfc1fbd add configuration protocol ports to top module for memory bank organization 2020-06-11 19:31:13 -06:00
tangxifan c00653961e minor format fix in documentation 2020-06-11 19:31:13 -06:00
tangxifan ad7422359d deploy compact constant values in Verilog codes 2020-06-11 19:31:13 -06:00
tangxifan 0931eccbf6 update documentation for the fast configuration options 2020-06-11 19:31:13 -06:00
tangxifan fe2ba7d50a update documentation for standalone configuration protocol 2020-06-11 19:31:13 -06:00
tangxifan c456ef4d00 deploy the standalone preconfig testcase to CI 2020-06-11 19:31:13 -06:00
tangxifan 2def059b5b add standalone configuration protocol to pre config test cases 2020-06-11 19:31:12 -06:00
tangxifan 1fedd00912 deploy the flatten configuration memory testcase to CI 2020-06-11 19:31:12 -06:00
tangxifan 8ec8ac4118 bug fixed in flatten memory organization. Passed verification 2020-06-11 19:31:12 -06:00
tangxifan 5f6a790eff add new test cases for the standalone memory configuration protocol 2020-06-11 19:31:12 -06:00
tangxifan 8b5b221a21 add new architecture for standalone memory organization 2020-06-11 19:31:12 -06:00
tangxifan b9aac3cbdf updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol 2020-06-11 19:31:12 -06:00
tangxifan fbe05963e0 add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol) 2020-06-11 19:31:12 -06:00