23bcad0678
use more robust net builder in inter tile connections
2020-06-30 10:49:17 -06:00
025d4a3599
use efficient net builder in top module connection builder
2020-06-29 23:28:26 -06:00
e7d5736269
add profile time to top module builder for better spot on runtime/memory overhead sources
2020-06-29 23:17:03 -06:00
57e6c84252
add reserve net sources and sinks to module manager
2020-06-29 22:49:11 -06:00
66746f69da
optimizing memory efficiency by reserving nets in module manager
2020-06-29 21:27:43 -06:00
e9937954f2
optimizing the constant writing in Verilog for single bits
2020-06-29 12:29:25 -06:00
9d32a5b81f
add alias name support for fabric key
2020-06-27 14:59:53 -06:00
ebf5636e7b
add verbose output to edge sorting for GSBs
2020-06-26 17:10:51 -06:00
aded675633
rename files in fpga bitstream library to be consistent with conventions
2020-06-21 13:06:39 -06:00
d526f08782
deploy bitstream reader in openfpga shell
2020-06-20 18:48:19 -06:00
675a59ecb8
Move fpga_bitstream to the libopenfpga library and add XML reader
2020-06-20 18:25:17 -06:00
5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
4f7e8020a8
minor fix on the format of arch bitstream writer
2020-06-17 00:08:28 -06:00
b91c30191a
add input and output net echo in arch bitstream database
2020-06-17 00:04:55 -06:00
19c0b57df6
ignore invalid nets when decoding bitstream
2020-06-16 22:26:36 -06:00
9d0e002532
echo path in architecture bitstream database
2020-06-16 21:29:45 -06:00
559564c333
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
2020-06-12 17:31:14 -06:00
a5055e9d26
add support about loading external fabric key
2020-06-12 13:03:11 -06:00
9dbf536306
add shuffled configurable children support for top module
2020-06-12 11:16:53 -06:00
cf9c3b0f44
add write fabric to test cases
2020-06-12 10:50:23 -06:00
3499b4d3e7
add fabric key writer for top-level module
2020-06-12 10:41:34 -06:00
278acee216
bug fix for 'build_fabric' command
2020-06-11 23:59:24 -06:00
9167b288b6
add options for fabric key
2020-06-11 21:50:46 -06:00
8a4ec85c39
add configurable children-related methods to module manager
2020-06-11 21:44:25 -06:00
58807bfcb3
remove simulation settings from openfpga arch data structure
2020-06-11 19:31:16 -06:00
96b58dfdbb
use new simulation setting command in openfpga shell
2020-06-11 19:31:15 -06:00
4a2f6dfae2
add read/write simulation setting commands to openfpga shell
2020-06-11 19:31:15 -06:00
3c10af7f2b
bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
2020-06-11 19:31:14 -06:00
8267dad8ef
add decoder support for Z signals
2020-06-11 19:31:14 -06:00
5368485bd6
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
2020-06-11 19:31:14 -06:00
c85ccceac7
try bug fixing in memory bank configuration protocol
2020-06-11 19:31:14 -06:00
0bee70bee6
finish memory bank configuration protocol support.
2020-06-11 19:31:13 -06:00
e14c39e14c
update Verilog full testbench generation to support memory bank configuration protocol
2020-06-11 19:31:13 -06:00
51e1559352
add fabric bitstream support for memory bank configuration protocol
2020-06-11 19:31:13 -06:00
0e16ee1030
add configuration bus nets for memory bank decoders at top module
2020-06-11 19:31:13 -06:00
fa8dfc1fbd
add configuration protocol ports to top module for memory bank organization
2020-06-11 19:31:13 -06:00
ad7422359d
deploy compact constant values in Verilog codes
2020-06-11 19:31:13 -06:00
8ec8ac4118
bug fixed in flatten memory organization. Passed verification
2020-06-11 19:31:12 -06:00
b9aac3cbdf
updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
2020-06-11 19:31:12 -06:00
fbe05963e0
add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
2020-06-11 19:31:12 -06:00
d2d443a988
start developing memory bank and standalone configuration protocol
2020-06-11 19:31:12 -06:00
9e176b8d38
add fast configuration stats to log
2020-06-11 19:31:12 -06:00
8b3e79766c
add fast configuration option to fpga_verilog to speed up full testbench simulation
2020-06-11 19:31:12 -06:00
b5e5182f52
frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
2020-06-11 19:31:11 -06:00
31c9a011dd
keep bug fixing for arch decoders
2020-06-11 19:31:11 -06:00
bdc9efb38f
bug fix in top-level testbench for frame-based decoders
2020-06-11 19:31:11 -06:00
986956e474
bug fix for arch decoder Verilog codes. Now Modelsim compiles ok.
2020-06-11 19:31:11 -06:00
6a72c66eb8
bug fixed for frame-based configuration memory in top-level full testbench
2020-06-11 19:31:11 -06:00
8aa665b3b2
bug fix in the Verilog codes for frame decoders
2020-06-11 19:31:10 -06:00
8298bbff78
bug fixed in the fabric bitstream for frame-based configurable memories.
2020-06-11 19:31:10 -06:00
tangxifan
ganeshgore