tangxifan
|
23aef96d3a
|
add behavioral verilog test case to Travis CI
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2020-04-12 19:55:47 -06:00 |
|
tangxifan
|
11e9014542
|
add notes about debugging the aib FPGA
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2020-04-12 19:07:53 -06:00 |
|
tangxifan
|
a614e5aad9
|
add long adder chain to Travis CI
|
2020-04-12 15:43:19 -06:00 |
|
tangxifan
|
f71a85a1d4
|
add test cases on different routing multiplexer circuit designs to Travis CI
|
2020-04-12 15:39:45 -06:00 |
|
tangxifan
|
214d98fbcd
|
add register chain and scan chain to Travis CI
|
2020-04-12 15:28:22 -06:00 |
|
tangxifan
|
148cc74d6a
|
add io test cases to Travis CI
|
2020-04-12 15:01:47 -06:00 |
|
tangxifan
|
da5af8f0e0
|
try to add aib test case. bug found
|
2020-04-12 14:54:45 -06:00 |
|
tangxifan
|
28cb412359
|
add test case of wide BRAM 16k to Travis CI
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2020-04-12 14:37:08 -06:00 |
|
tangxifan
|
5d665aa04b
|
reshape bram test case
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2020-04-12 14:32:09 -06:00 |
|
tangxifan
|
600a48edc7
|
add test case of BRAM to Travis CI
|
2020-04-12 14:27:05 -06:00 |
|
tangxifan
|
2444752de8
|
add untileable test case to Travis CI
|
2020-04-12 14:08:24 -06:00 |
|
tangxifan
|
d806ad3148
|
add testcases using openfpga_shell in openfpga_flow
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2020-04-12 12:54:21 -06:00 |
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tangxifan
|
68fd296e14
|
add more test vpr architecture to regression tests
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2020-04-12 12:49:16 -06:00 |
ganeshgore
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80bdb41df6
|
Updated task file to run formal verification
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2020-04-11 18:30:21 -06:00 |
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tangxifan
|
49ddbf98c3
|
add more testing architecture to openfpga_flow
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2020-04-11 18:01:09 -06:00 |
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tangxifan
|
130b78ca74
|
update arch in openfpga_flow
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2020-04-11 18:00:37 -06:00 |
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ganeshgore
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f6b3c5854a
|
Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
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2020-04-11 16:45:22 -06:00 |
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ganeshgore
|
8ea272dc2c
|
Patched the OpenFPGA shell execution bug
|
2020-04-08 21:28:14 -06:00 |
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ganeshgore
|
583a4d8767
|
Fixed bug in openfpga_flow script
|
2020-04-08 12:04:08 -06:00 |
|
ganeshgore
|
e1db4df744
|
Created task for FPGA shell run
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2020-04-06 00:35:07 -06:00 |
|
ganeshgore
|
ea4122a8a4
|
Updated openfpga_flow and task file to support sheel run
|
2020-04-06 00:34:36 -06:00 |
|
ganeshgore
|
7f98ecc8a6
|
OpenFPGA shell run test script template
|
2020-04-06 00:32:43 -06:00 |
|
ganeshgore
|
eb3b02277a
|
Added XML and benchmarks for testing
|
2020-04-06 00:32:06 -06:00 |
|
ganeshgore
|
77f7e13ba7
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-04-05 20:59:10 -06:00 |
|
ganeshgore
|
d1d3446568
|
backedup partial upgrade for fpga_flow script
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2020-04-05 11:36:24 -06:00 |
|
tangxifan
|
2f38b5cbc2
|
Merge branch 'refactoring' into dev
|
2020-03-08 16:23:20 -06:00 |
|
tangxifan
|
b219b096ee
|
hotfix on removing dangling inputs from GSB, which are CLB direct output
|
2020-03-08 13:54:49 -06:00 |
AurelienUoU
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c51001c853
|
Add compilation verification task in openfpga_flow
|
2020-01-23 13:13:23 -07:00 |
|
ganeshgore
|
cd69f1870d
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2020-01-23 10:07:36 -07:00 |
|
ganeshgore
|
46bb5ef9d0
|
Added disp option in openfpga_flow, Default is --nodisp
|
2020-01-23 10:04:38 -07:00 |
|
AurelienUoU
|
85c9f26a9f
|
Update documentation about cmake version and graphical interface
|
2020-01-22 20:46:49 -07:00 |
|
ganeshgore
|
f0bed1244c
|
Added blif file folding before VPR run
|
2020-01-09 16:50:34 -07:00 |
|
ganeshgore
|
74b650e9e1
|
Added fpga_x2p_duplicate_grid_pin option
|
2019-12-30 12:25:28 -07:00 |
|
ganeshgore
|
d1e260f54f
|
Spice related option added
|
2019-12-30 12:16:04 -07:00 |
|
tangxifan
|
ef9ed2ccbc
|
added duplicate_grid_pin test case
|
2019-12-26 15:08:31 -07:00 |
|
AurelienUoU
|
09fd2afa9c
|
Adding heterogeneous synthesis requirements
|
2019-12-03 16:09:26 -07:00 |
|
AurelienUoU
|
32176eb352
|
Adding EPFL benchmark task for openfpga_flow
|
2019-12-03 14:31:53 -07:00 |
|
AurelienUoU
|
2f14716f13
|
Adding DPRAM behavioural Verilog netlist and its TB
|
2019-12-03 13:58:20 -07:00 |
|
tangxifan
|
96733f9ea8
|
add minor comments in task file for modelsim regression tests
|
2019-11-16 22:34:03 -07:00 |
|
Ganesh Gore
|
3f235a16f9
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-11-16 19:14:34 -07:00 |
|
Ganesh Gore
|
6bb11918dc
|
Updated modelsim and collected result
|
2019-11-16 19:10:04 -07:00 |
|
tangxifan
|
a13f406918
|
tweaking mcnc_big20 task run for modelsim
|
2019-11-16 18:00:55 -07:00 |
|
Ganesh Gore
|
00ec36c1af
|
Added Modelsim error check in log
|
2019-11-16 13:18:13 -07:00 |
|
Ganesh Gore
|
373dbe0718
|
First draft for multithreaded Modelsim simulation
|
2019-11-16 01:06:09 -07:00 |
|
Ganesh Gore
|
f05aede868
|
Added task support for modelsim script
|
2019-11-15 23:23:15 -07:00 |
|
Ganesh Gore
|
f52eaef622
|
Updated flow script and skipped travis upload on failure test setup.
|
2019-11-15 14:35:15 -07:00 |
|
tangxifan
|
4df6402241
|
add python script for batch simulations
|
2019-11-15 14:23:03 -07:00 |
|
tangxifan
|
d391983e8c
|
passing regression test on dpram benchmarks
|
2019-11-07 14:57:46 -07:00 |
|
tangxifan
|
56b4ee008e
|
add test for heterogeneous FPGA and fix bugs
|
2019-11-06 17:45:11 -07:00 |
|
tangxifan
|
4ea5756be6
|
bug fixed for std cell MUX2 architecture and add the case to regression tests
|
2019-11-06 16:06:47 -07:00 |