4dedee4011
[test] add a new test case to basic reg test to validate write_fabric_pin_physical_location command
2024-04-11 12:59:13 -07:00
f0639b4567
[test] add new testcase to basic reg test
2024-03-29 11:56:11 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
b182b47d0b
[test] use a timing-focus tool path for a testcase
2023-12-12 13:28:35 -08:00
6a5df804b9
[test] add new testcase to reg test
2023-12-08 13:46:54 -08:00
d78f18d235
[test] add new testcase
2023-11-13 14:11:34 -08:00
8e875f3453
[test] add a new test case to validate the new feature
2023-11-02 21:08:36 -07:00
c6f33bcd7f
[test] add new tests to cover the new features
2023-10-06 18:41:57 -07:00
7d83fc914c
[core] ad a new test case
2023-10-06 18:31:54 -07:00
5aa206e616
[core] fixed some bugs
2023-09-25 22:27:24 -07:00
60b8c396dc
[test] add a new test
2023-09-25 21:25:21 -07:00
663c9c9fa1
[test] add a new test to validate the tile port merge feature
2023-09-25 18:34:34 -07:00
195aa7a9a8
[test] developing new test to increase coverage on module renaming
2023-09-23 12:40:20 -07:00
11e976ec92
[test] add a new test to validate renaming on fpga top/core modules
2023-09-17 17:38:37 -07:00
0ef1e0bde5
[test] add a new test to validate renaming rules
2023-09-17 13:29:12 -07:00
559fa45d89
[test] add a new test to validate module renaming using index
2023-09-16 17:55:52 -07:00
56cedf6c8b
[test] added a new test case to validate the support on different wire segment distribution on X and Y
2023-08-22 11:20:14 -07:00
1b132fd667
[test] add a new testcase to validate the support on different routing channel width on X and Y
2023-08-22 11:06:12 -07:00
15a8d8a76a
[test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation
2023-08-18 21:59:06 -07:00
5f6050d404
[test] add a new test to validate combo: group tile, tile annotation and subtile
2023-08-18 21:48:40 -07:00
5ac8919ce0
[test] add a new testcase to validate subtile with tile annotations
2023-08-18 21:37:15 -07:00
e82e4f487e
[test] add a new test to validate io subtile support
2023-08-18 11:13:34 -07:00
913c232556
[test] deploy new test to basic reg test
2023-08-17 14:54:24 -07:00
16f102f4c1
[test] deploy new tests to basic regression tests
2023-08-11 13:07:41 -07:00
b7048d3dc8
[test] adding new tests to validate group config block
2023-08-03 22:30:41 -07:00
3d56bd0ff2
[test] deploy the new test to ci
2023-07-27 17:03:55 -07:00
46e58a56cb
[test] added a new test case to validate clock network when using the tile modules
2023-07-27 16:39:48 -07:00
e9f2adf3f9
[test] add a new testcase to validate carry chain connections when using tile modules
2023-07-27 16:06:43 -07:00
1ea8a33d4b
[test] add a new testcase to validate global tile connections on tile modules
2023-07-27 15:57:38 -07:00
a2848940df
[test] add a new testcase to ease debugging
2023-07-26 22:32:03 -07:00
5685fbd5e8
[test] adding a new test case to validate the tile modules on 4x4 fabric
2023-07-26 22:17:39 -07:00
0db4ef62e8
[test] add a new test for tile-based fabric: using preconfig testbenches
2023-07-25 15:48:14 -07:00
82fe63297a
[test] add a new test for top-left tile grouping
2023-07-19 11:22:36 -07:00
930d98f2af
[test] deploy new tests
2023-07-08 21:52:16 -07:00
919d6d8608
[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches
2023-06-25 22:49:51 -07:00
962ba67e36
[test] adding new tests to validate fpga core wrapper naming rules
2023-06-23 14:47:21 -07:00
efc9bf9907
[test] added new test case to validate bitstream generation
2023-06-19 12:40:37 -07:00
97b089ae3c
[test] added new testcases to validate fpga core wrapper
2023-06-18 21:01:37 -07:00
e1feebc96d
[core] fixing bugs on pcf and bgf support for mock efpga wrapper
2023-05-26 21:54:08 -07:00
812553e13d
[test] adding more test cases
2023-05-25 20:17:23 -07:00
df771cb33a
[test] add a new testcase for subtile and deploy it to basic regression test
2023-05-03 15:41:29 +08:00
f06248a1b0
[test] add a new testcase to validate the ccff v2
2023-04-24 14:55:22 +08:00
02e964b16f
[test] add a new test case for ccffv2
2023-04-22 15:41:19 +08:00
087636cefa
[test] deploy new test to regression tests
2023-04-20 15:06:47 +08:00
7d333b3669
[test] add a new test for clock network: validate full testbench is working
2023-04-20 10:36:08 +08:00
780dec6b1b
[test] add a new test to validate the programmable clock arch
2023-02-28 21:46:57 -08:00
4f6b8c0905
Updated regression tests
2023-02-11 22:11:06 -07:00
8174f53796
[test] deploy new test to fpga bitstream regression
2023-01-24 15:42:01 -08:00
95dd4fd535
[test] deploy new test to basic regression tests
2023-01-18 18:17:53 -08:00
5aa85d82e6
[test] deploy the new test to basic regression tests
2023-01-13 22:07:45 -08:00
bbf83101be
[test] deploy new test to ci
2023-01-11 17:11:28 -08:00
43cb498827
[test] deploy new tests to basic regression tests
2023-01-01 17:07:25 -08:00
93b020b0b3
[test] deploy new test to basic regression tests
2022-12-30 18:26:22 -08:00
c33b9f1b9b
[script] enable eval mode in tcl reg test
2022-12-02 12:07:27 -08:00
156fac9fec
[ci] deploy tcl test to ci
2022-12-02 11:46:14 -08:00
97c72c73f1
[test] add a small test to validate tcl integration
2022-12-02 11:43:46 -08:00
609e096b1a
[test] added a new test to validate explicit port direction in pin table support
2022-10-17 15:25:19 -07:00
aa78981e37
[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
2022-10-17 11:18:21 -07:00
5cf315958d
[test] deploy new test to basic regression tests
2022-10-13 11:17:34 -07:00
13c819bb28
[ci] deply new test to ci
2022-10-01 11:04:08 -07:00
ce0fbe1765
[test] fixed a few bugs
2022-09-29 15:32:31 -07:00
36603f9772
Merge branch 'master' into vtr_upgrade
2022-09-20 21:08:06 -07:00
e0f632cc9c
[test] fixed a bug
2022-09-20 20:29:34 -07:00
645d8df7b9
[test] fixed a bug
2022-09-20 20:09:41 -07:00
9042fc2422
[test] now reg test should show diff details when failed
2022-09-20 19:32:34 -07:00
da157ed5de
[test] debugging git-diff
2022-09-20 15:31:39 -07:00
6a896a9845
[test] debugging
2022-09-20 14:08:22 -07:00
ecfdc4a83a
[test] debugging
2022-09-20 13:51:32 -07:00
bdcdc7d294
[test] Now git diff in basic regression tests should capture the changes on golden outputs
2022-09-20 13:36:31 -07:00
373566416c
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
2022-09-16 16:47:21 -07:00
a2e22787c2
[test] deploy the new test cases to the basic regression tests
2022-09-16 10:31:15 -07:00
91fe27ff66
[test] deploy new test to ci
2022-09-09 17:00:28 -07:00
95d7a17b3c
Merge branch 'master' into vtr_upgrade
2022-09-09 14:32:42 -07:00
a840aeea7a
[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
2022-09-08 16:27:11 -07:00
56619f9a47
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
2022-09-07 15:04:05 -07:00
93ab992187
[test] update golden outputs without time stamps
2022-09-06 14:59:00 -07:00
9e1abf5898
Merge branch 'master' into vtr_upgrade
2022-09-01 21:39:14 -07:00
c48f750f86
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
2022-09-01 20:10:29 -07:00
71ad0721a1
Merge branch 'master' into vtr_upgrade
2022-08-31 13:56:17 -07:00
201bca8968
[test] typo
2022-08-30 08:59:20 -07:00
5f88b9a226
[test] typo
2022-08-29 22:41:15 -07:00
0b5bdcdbb1
[test] deploy new test to basic regression tests
2022-08-29 22:07:56 -07:00
8d6682c28b
[test] fixed a bug when removing previous runs
2022-08-25 16:20:18 -07:00
6ce1d4804c
[test] deploy new test case to basic regression tests
2022-08-01 21:05:05 -07:00
347a29f27c
Fix test name in basic regression test script.
2022-07-20 21:05:31 -07:00
cfc0d08060
Add constrain_pin_location command in openfpga; add full flow test.
2022-07-20 11:51:00 -07:00
9832722056
[test] now add QuickLogic memory bank to fpga bitstream regression tests
2022-05-25 11:42:32 +08:00
86347a9d49
[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
2022-05-25 11:19:49 +08:00
7d694acf32
[test] debugging basic reg test paths
2022-05-23 11:21:36 +08:00
b41cbad5d3
[test] force to run git diff under root directory
2022-05-23 10:32:43 +08:00
488a934097
[test] give abs path for git diff in basic regression tests
2022-05-23 09:12:33 +08:00
0dc7caf3b7
[test] now regression test script supports remove all run dir through command-line options
2022-05-22 13:15:39 +08:00
751d87b8e3
[test] fix a bug in detect changes in golden netlists
2022-05-22 13:06:47 +08:00
d7e854eae7
[test] deploy new test to ci
2022-05-09 17:23:57 +08:00
522982c9ba
Adde vtr_benchmarks_template for demo
2022-05-06 22:40:36 -06:00
1e243650b9
Added option to copy example projects
2022-05-03 14:06:16 -06:00
21c3dbf611
Added regression for template project
2022-05-02 23:23:45 -06:00
9bd66d531e
[Test] Deploy the new test case to basic regression tests
2022-04-13 16:06:27 +08:00
3e3a65223c
[Test] Deploy new test case to basic regression tests
2022-03-20 11:04:07 +08:00
a615c9d4e3
[Test] Rename test cases
2022-02-24 09:43:41 -08:00
tangxifan
chungshien
Ganesh Gore
taoli4rs