tangxifan
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1baee10e61
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Merge pull request #298 from lnis-uofu/micro_benchmarks
Micro benchmarks addition and testing for FPGAs with DSP blocks
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2021-04-24 17:55:38 -06:00 |
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tangxifan
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62dc5a3856
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[Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes
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2021-04-24 16:02:24 -06:00 |
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tangxifan
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b7da22501c
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[Test] Deply new test to regression test
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2021-04-24 15:55:05 -06:00 |
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tangxifan
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5adffad602
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[Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!!
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2021-04-24 15:49:53 -06:00 |
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tangxifan
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80f98328df
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[Test] Update test settings for architecture with fracturable DSP blocks
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2021-04-24 15:16:50 -06:00 |
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tangxifan
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8b8096f3a8
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[HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block
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2021-04-24 14:57:09 -06:00 |
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tangxifan
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a3a98fa21d
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[Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition
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2021-04-24 14:56:10 -06:00 |
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tangxifan
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148da80869
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[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes
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2021-04-24 14:53:29 -06:00 |
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tangxifan
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4f454abfde
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[Arch] Add a new architecture using fracturable 16-bit DSP blocks
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2021-04-24 14:01:42 -06:00 |
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tangxifan
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272d1fffb7
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[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks
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2021-04-24 13:30:46 -06:00 |
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tangxifan
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ddcdb35b28
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[Arch] Bug fix in single-mode 8-bit DSP architectures
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2021-04-24 13:30:03 -06:00 |
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tangxifan
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1c6b9a23d7
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[Test] Add new test for multi-mode 16-bit DSP blocks
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2021-04-24 13:29:29 -06:00 |
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tangxifan
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0709e5bb81
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[Tool] Fixed a bug in the routing trace finder for direct connections inside repacker
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2021-04-24 13:27:44 -06:00 |
Parnabrita Mondal
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cc92c27fde
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Update compile.rst
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2021-04-24 14:01:52 +05:30 |
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tangxifan
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c44688739d
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[HDL] Add verilog netlist for the fracturable 16-bit multiplier blocks
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2021-04-23 22:12:26 -06:00 |
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tangxifan
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09cc7f0007
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[Script] Enable constant net routing for heterogeneous FPGAs
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2021-04-23 20:44:36 -06:00 |
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tangxifan
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189c94ff19
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[Test] Deploy new mac benchmarks to tests
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2021-04-23 20:44:14 -06:00 |
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tangxifan
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200b6d39a6
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[Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit
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2021-04-23 20:36:28 -06:00 |
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tangxifan
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671394ec2c
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[Benchmark] Add microbenchmarks for mac with different sizes for DSP testing
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2021-04-23 20:33:43 -06:00 |
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tangxifan
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5ce28158bd
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Merge pull request #297 from lnis-uofu/iwls2005
Enable constant net routing for VTR benchmarks
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2021-04-23 16:52:35 -06:00 |
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tangxifan
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1db7719045
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Merge branch 'master' into iwls2005
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2021-04-23 15:11:14 -06:00 |
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tangxifan
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cbb7d41b6e
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[Script] Enable constant net routing for VTR benchmarks
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2021-04-23 14:15:13 -06:00 |
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tangxifan
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f01b43c0fd
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Merge pull request #296 from lnis-uofu/iwls2005
Unlock flexible FF mapping and enable IWLS'2005 benchmark
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2021-04-22 20:31:40 -06:00 |
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tangxifan
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784713e88a
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[Test] Add golden results for IWLS2005 as a simple QoR check
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2021-04-22 19:27:31 -06:00 |
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tangxifan
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a16896054d
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[Script] Enable constant net routing for iwls benchmarks
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2021-04-22 19:16:32 -06:00 |
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tangxifan
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56948244bc
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[Tool] Patch a critical bug in pb pin fixup
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2021-04-22 16:19:54 -06:00 |
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tangxifan
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1dcb8e39a9
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[Test] Unlock more IWLS'2005 benchmarks in testing
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2021-04-22 09:23:33 -06:00 |
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tangxifan
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61a473e479
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[Test] Unlock more IWLS'2005 benchmarks under testing thanks to flexible FF mapping support
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2021-04-21 22:56:19 -06:00 |
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tangxifan
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5a519390ff
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[HDL] Enriched DFF model in yosys technology library
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2021-04-21 22:49:05 -06:00 |
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tangxifan
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ce6018e123
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[Arch] Enriched DFF model to support active-low/high FFs
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2021-04-21 22:48:31 -06:00 |
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tangxifan
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adfea88be2
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[HDL] Rename multi-mode DFF module
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2021-04-21 20:06:03 -06:00 |
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tangxifan
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62497549b6
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[HDL] Add multi-mode DFF module
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2021-04-21 20:04:40 -06:00 |
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tangxifan
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3a5c26c6a1
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[Test] Update IWLS test by using new architecture and customize DFF techmap
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2021-04-21 19:51:25 -06:00 |
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tangxifan
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8cbea6a268
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[HDL] Add technology library for customizable DFF synthesis
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2021-04-21 19:50:51 -06:00 |
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tangxifan
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3d615e1516
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[Script] Add yosys script supporting customize DFF/BRAM/DSP mapping
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2021-04-21 19:50:07 -06:00 |
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tangxifan
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9d9840d9b7
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[Arch] Add architecture using multi-mode DFFs
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2021-04-21 19:49:48 -06:00 |
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tangxifan
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c198273378
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Merge pull request #295 from lnis-uofu/multi_clock
Patches on multi-clock support in repacking stage
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2021-04-21 15:22:53 -06:00 |
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tangxifan
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2e1cc5499d
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[Doc] Add disclaimer for limitations when using repack pin constraints
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2021-04-21 14:14:54 -06:00 |
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tangxifan
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8046b16c15
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[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
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2021-04-21 14:04:34 -06:00 |
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tangxifan
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b203ef7bc2
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[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
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2021-04-21 14:03:51 -06:00 |
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tangxifan
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96ce6b545f
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[Tool] Patch repack to consider design constraints for pins that are not equivalent
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2021-04-21 13:53:08 -06:00 |
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tangxifan
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12f27cf117
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Merge pull request #294 from lnis-uofu/mux_default_path
Support customizable default path in bitstream generation for any interconnect inside pb_type
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2021-04-19 18:29:03 -06:00 |
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tangxifan
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2fa370d7d5
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[Test] Patch regression tests for fpga bitstream
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2021-04-19 17:15:14 -06:00 |
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tangxifan
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9b3dcc65bd
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[Doc] Add new bitstream setting syntex 'interconnect' to documentation
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2021-04-19 16:37:21 -06:00 |
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tangxifan
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17fb532ffa
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Merge branch 'master' into mux_default_path
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2021-04-19 16:23:44 -06:00 |
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tangxifan
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64163edbe6
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[Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting
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2021-04-19 16:15:25 -06:00 |
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tangxifan
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578d81b67a
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[Test] Patch task configuration file
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2021-04-19 16:15:00 -06:00 |
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tangxifan
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f7767ff4df
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Merge pull request #284 from lnis-uofu/tutorials
Tutorials
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2021-04-19 16:00:16 -06:00 |
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tangxifan
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18eb5c9de9
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[Test] Deploy new test to CI
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2021-04-19 15:56:41 -06:00 |
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tangxifan
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5976cc0a1c
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[Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection
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2021-04-19 15:54:18 -06:00 |