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Merge pull request #297 from lnis-uofu/iwls2005 

Enable constant net routing for VTR benchmarks
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tangxifan 2021-04-23 16:52:35 -06:00 committed by GitHub
parent f01b43c0fd 1db7719045
commit 5ce28158bd
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1 changed files with 2 additions and 2 deletions
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openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga
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@ -1,8 +1,8 @@
# Run VPR for the 'and' design
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
# This is due to the Fc_in of clock port is set to 0 for global wiring
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH}
# The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}