Merge pull request #296 from lnis-uofu/iwls2005
Unlock flexible FF mapping and enable IWLS'2005 benchmark
This commit is contained in:
tangxifan
GitHub
commit
f01b43c0fd
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@ -96,20 +96,49 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
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/* Find the net mapped to this pin in clustering results*/
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ClusterNetId cluster_net_id = clustering_ctx.clb_nlist.block_net(blk_id, j);
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/* Ignore those net have never been routed */
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/* Ignore those net have never been routed: this check is valid only
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* when both packer has mapped a net to the pin and the router leaves the pin to be unmapped
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* This is important because we cannot bypass when router forces a valid net to be mapped
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* and the net remapping has to be considered
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*/
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if ( (ClusterNetId::INVALID() != cluster_net_id)
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&& (ClusterNetId::INVALID() == routing_net_id)
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&& (true == clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id))) {
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VTR_LOGV(verbose,
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"Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' as it is not routed\n",
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clustering_ctx.clb_nlist.block_pb(blk_id)->name,
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grid_coord.x(), grid_coord.y(),
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clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name,
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get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name,
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get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number
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);
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continue;
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}
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/* Ignore used in local cluster only, reserved one CLB pin */
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if ( (ClusterNetId::INVALID() != cluster_net_id)
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&& (0 == clustering_ctx.clb_nlist.net_sinks(cluster_net_id).size())) {
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VTR_LOGV(verbose,
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"Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' as it is a local net inside the cluster\n",
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clustering_ctx.clb_nlist.block_pb(blk_id)->name,
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grid_coord.x(), grid_coord.y(),
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clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name,
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get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name,
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get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number
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);
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continue;
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}
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/* If matched, we finish here */
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if (routing_net_id == cluster_net_id) {
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VTR_LOGV(verbose,
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"Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' as it matches cluster routing\n",
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clustering_ctx.clb_nlist.block_pb(blk_id)->name,
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grid_coord.x(), grid_coord.y(),
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clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name,
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get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name,
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get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number
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);
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continue;
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}
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@ -0,0 +1,105 @@
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# Yosys synthesis script for ${TOP_MODULE}
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#########################
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# Parse input files
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#########################
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# Read verilog files
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${READ_VERILOG_FILE}
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# Read technology library
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read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
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#########################
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# Prepare for synthesis
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#########################
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# Identify top module from hierarchy
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hierarchy -check -top ${TOP_MODULE}
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# - Convert process blocks to AST
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proc
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# Flatten all the gates/primitives
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flatten
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# Identify tri-state buffers from 'z' signal in AST
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# with follow-up optimizations to clean up AST
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tribuf -logic
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opt_expr
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opt_clean
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# demote inout ports to input or output port
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# with follow-up optimizations to clean up AST
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deminout
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opt
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opt_expr
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opt_clean
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check
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opt
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wreduce -keepdc
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peepopt
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pmuxtree
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opt_clean
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########################
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# Map multipliers
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# Inspired from synth_xilinx.cc
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#########################
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# Avoid merging any registers into DSP, reserve memory port registers first
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memory_dff
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wreduce t:$mul
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techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS}
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select a:mul2dsp
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setattr -unset mul2dsp
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opt_expr -fine
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wreduce
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select -clear
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chtype -set $mul t:$__soft_mul# Extract arithmetic functions
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#########################
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# Run coarse synthesis
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#########################
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# Run a tech map with default library
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techmap
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alumacc
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share
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opt
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fsm
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# Run a quick follow-up optimization to sweep out unused nets/signals
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opt -fast
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# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells
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memory -nomap
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opt_clean
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#########################
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# Map logics to BRAMs
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#########################
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memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
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techmap -map ${YOSYS_BRAM_MAP_VERILOG}
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opt -fast -mux_undef -undriven -fine
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memory_map
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opt -undriven -fine
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#########################
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# Map flip-flops
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#########################
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techmap -map ${YOSYS_DFF_MAP_VERILOG}
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opt_expr -mux_undef
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simplemap
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opt_expr
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opt_merge
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opt_rmdff
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opt_clean
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opt
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#########################
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# Map LUTs
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#########################
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abc -lut ${LUT_SIZE}
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#########################
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# Check and show statisitics
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#########################
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hierarchy -check
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stat
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#########################
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# Output netlists
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#########################
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opt_clean -purge
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write_blif ${OUTPUT_BLIF}
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@ -0,0 +1,333 @@
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k6_N10_40nm.xml
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- General purpose logic block
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- K = 6, N = 10, I = 40
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
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<design_technology type="cmos" topology="OR"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" size="1"/>
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<port type="input" prefix="b" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
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<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="sel" size="1"/>
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<port type="input" prefix="selb" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="MULTI_MODE_DFFSRQ" prefix="MULTI_MODE_DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="S" lib_name="SET" size="1"/>
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<port type="input" prefix="R" lib_name="RST" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="C" lib_name="CK" size="1"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="0"/>
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</circuit_model>
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<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
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<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="true" circuit_model_name="buf4"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
|
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<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
|
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<port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
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<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
|
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<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
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<port type="sram" prefix="sram" size="64"/>
|
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
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</circuit_model>
|
||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
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<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
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<design_technology type="cmos"/>
|
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
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<port type="input" prefix="D" size="1"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="output" prefix="QN" size="1"/>
|
||||
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
<port type="input" prefix="outpad" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/adder.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="a" lib_name="A" size="1"/>
|
||||
<port type="input" prefix="b" lib_name="B" size="1"/>
|
||||
<port type="input" prefix="cin" lib_name="CI" size="1"/>
|
||||
<port type="output" prefix="sumout" lib_name="SUM" size="1"/>
|
||||
<port type="output" prefix="cout" lib_name="CO" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="dpram_1024x8" prefix="dpram_1024x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="waddr" size="10"/>
|
||||
<port type="input" prefix="raddr" size="10"/>
|
||||
<port type="input" prefix="data_in" size="8"/>
|
||||
<port type="input" prefix="wen" size="1"/>
|
||||
<port type="input" prefix="ren" size="1"/>
|
||||
<port type="output" prefix="data_out" size="8"/>
|
||||
<port type="clock" prefix="clk" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="mult_36x36" prefix="mult_36x36" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/mult_36x36.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/mult_36x36.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="A" lib_name="A" size="36"/>
|
||||
<port type="input" prefix="B" lib_name="B" size="36"/>
|
||||
<port type="output" prefix="Y" lib_name="out" size="72"/>
|
||||
<!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
|
||||
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
</circuit_model>
|
||||
</circuit_library>
|
||||
<configuration_protocol>
|
||||
<organization type="scan_chain" circuit_model_name="DFFR"/>
|
||||
</configuration_protocol>
|
||||
<connection_block>
|
||||
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</connection_block>
|
||||
<switch_block>
|
||||
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</switch_block>
|
||||
<routing_segment>
|
||||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<direct_connection>
|
||||
<direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
||||
</direct_connection>
|
||||
<tile_annotations>
|
||||
<global_port name="op_clk" tile_port="clb.clk" is_clock="true" default_val="0">
|
||||
<tile name="clb" port="clk"/>
|
||||
<tile name="memory" port="clk"/>
|
||||
</global_port>
|
||||
<global_port name="op_reset" is_reset="true" default_val="0">
|
||||
<tile name="clb" port="reset"/>
|
||||
</global_port>
|
||||
<global_port name="op_set" is_set="true" default_val="0">
|
||||
<tile name="clb" port="set"/>
|
||||
</global_port>
|
||||
</tile_annotations>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
|
||||
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
|
||||
<!-- physical pb_type binding in complex block CLB -->
|
||||
<!-- physical mode will be the default mode if not specified -->
|
||||
<pb_type name="clb">
|
||||
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
|
||||
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="MULTI_MODE_DFFSRQ" mode_bits="00"/>
|
||||
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
|
||||
<!-- Binding operating pb_type to physical pb_type -->
|
||||
<!-- Binding operating pb_types in mode 'n2_lut5' -->
|
||||
<pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
|
||||
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:4]"/>
|
||||
<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut5].ble5.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut5].ble5.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
|
||||
<pb_type name="clb.fle[n2_lut5].ble5.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
|
||||
<pb_type name="clb.fle[n2_lut5].ble5.ff[dffs].dffs" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
|
||||
<pb_type name="clb.fle[n2_lut5].ble5.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="10">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut5].ble5.ff[dffsn].dffsn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="01">
|
||||
<port name="SN" physical_mode_port="S"/>
|
||||
</pb_type>
|
||||
<!-- Binding operating pb_types in mode 'arithmetic' -->
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
|
||||
<!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:3]"/>
|
||||
<port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.ff[dffs].dffs" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="10">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.ff[dffsn].dffsn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="01">
|
||||
<port name="SN" physical_mode_port="S"/>
|
||||
</pb_type>
|
||||
<!-- Binding operating pb_types in mode 'ble6' -->
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
|
||||
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:5]"/>
|
||||
<port name="out" physical_mode_port="lut6_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.ff[dffs].dffs" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="10" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.ff[dffsn].dffsn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="01" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="SN" physical_mode_port="S"/>
|
||||
</pb_type>
|
||||
<!-- End physical pb_type binding in complex block clb -->
|
||||
|
||||
<!-- physical pb_type binding in complex block dsp -->
|
||||
<pb_type name="mult_36" physical_mode_name="mult_36x36" idle_mode_name="mult_36x36"/>
|
||||
<!-- Bind the primitive pb_type in the physical mode to a circuit model -->
|
||||
<pb_type name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" circuit_model_name="mult_36x36" mode_bits="00"/>
|
||||
|
||||
<!-- physical pb_type binding in complex block memory -->
|
||||
<pb_type name="memory[mem_1024x8_dp].mem_1024x8_dp" circuit_model_name="dpram_1024x8"/>
|
||||
<!-- END physical pb_type binding in complex block memory -->
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
|
|
@ -289,6 +289,34 @@ assign Q = q_reg;
|
|||
|
||||
endmodule //End Of Module
|
||||
|
||||
//-----------------------------------------------------
|
||||
// Function : A multi-functional D-type flip-flop with
|
||||
// - asynchronous reset
|
||||
// which can be switched between active-low and active hight
|
||||
// - asynchronous set which can be switched
|
||||
// which can be switched between active-low and active hight
|
||||
//-----------------------------------------------------
|
||||
module MULTI_MODE_DFFSRQ (
|
||||
input SET, // Set input
|
||||
input RST, // Reset input
|
||||
input CK, // Clock Input
|
||||
input D, // Data Input
|
||||
output Q, // Q output
|
||||
input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
|
||||
);
|
||||
|
||||
wire post_set = mode ? ~SET : SET;
|
||||
wire post_reset = mode ? ~RST : RST;
|
||||
|
||||
DFFSRQ FF_CORE (.SET(post_set),
|
||||
.RST(post_rst),
|
||||
.CK(CK),
|
||||
.D(D),
|
||||
.Q(Q)
|
||||
);
|
||||
|
||||
endmodule //End Of Module
|
||||
|
||||
//-----------------------------------------------------
|
||||
// Function : D-type flip-flop with
|
||||
// - asynchronous active high reset
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
# Run VPR for the 'and' design
|
||||
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
|
||||
# This is due to the Fc_in of clock port is set to 0 for global wiring
|
||||
#--write_rr_graph example_rr_graph.xml
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH}
|
||||
# The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,220 @@
|
|||
//-----------------------------
|
||||
// Dual-port RAM 1024x8 bit (8Kbit)
|
||||
// Core logic
|
||||
//-----------------------------
|
||||
module dpram_1024x8_core (
|
||||
input wclk,
|
||||
input wen,
|
||||
input [0:9] waddr,
|
||||
input [0:7] data_in,
|
||||
input rclk,
|
||||
input ren,
|
||||
input [0:9] raddr,
|
||||
output [0:7] data_out );
|
||||
|
||||
reg [0:7] ram[0:1023];
|
||||
reg [0:7] internal;
|
||||
|
||||
assign data_out = internal;
|
||||
|
||||
always @(posedge wclk) begin
|
||||
if(wen) begin
|
||||
ram[waddr] <= data_in;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge rclk) begin
|
||||
if(ren) begin
|
||||
internal <= ram[raddr];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
//-----------------------------
|
||||
// Dual-port RAM 1024x8 bit (8Kbit) wrapper
|
||||
// where the read clock and write clock
|
||||
// are combined to a unified clock
|
||||
//-----------------------------
|
||||
module dpram_1024x8 (
|
||||
input clk,
|
||||
input wen,
|
||||
input ren,
|
||||
input [0:9] waddr,
|
||||
input [0:9] raddr,
|
||||
input [0:7] data_in,
|
||||
output [0:7] data_out );
|
||||
|
||||
dpram_1024x8_core memory_0 (
|
||||
.wclk (clk),
|
||||
.wen (wen),
|
||||
.waddr (waddr),
|
||||
.data_in (data_in),
|
||||
.rclk (clk),
|
||||
.ren (ren),
|
||||
.raddr (raddr),
|
||||
.data_out (data_out) );
|
||||
|
||||
endmodule
|
||||
|
||||
//-----------------------------
|
||||
// 36-bit multiplier
|
||||
//-----------------------------
|
||||
module mult_36(
|
||||
input [0:35] A,
|
||||
input [0:35] B,
|
||||
output [0:71] Y
|
||||
);
|
||||
|
||||
assign Y = A * B;
|
||||
|
||||
endmodule
|
||||
|
||||
//-----------------------------
|
||||
// Native D-type flip-flop
|
||||
//-----------------------------
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module dff(
|
||||
output reg Q,
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
initial Q = INIT;
|
||||
case(|IS_C_INVERTED)
|
||||
1'b0:
|
||||
always @(posedge C)
|
||||
Q <= D;
|
||||
1'b1:
|
||||
always @(negedge C)
|
||||
Q <= D;
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
//-----------------------------
|
||||
// D-type flip-flop with active-high asynchronous reset
|
||||
//-----------------------------
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module dffr(
|
||||
output reg Q,
|
||||
input D,
|
||||
input R,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
initial Q = INIT;
|
||||
case(|IS_C_INVERTED)
|
||||
1'b0:
|
||||
always @(posedge C or posedge R)
|
||||
if (R == 1'b1)
|
||||
Q <= 1'b0;
|
||||
else
|
||||
Q <= D;
|
||||
1'b1:
|
||||
always @(negedge C or posedge R)
|
||||
if (R == 1'b1)
|
||||
Q <= 1'b0;
|
||||
else
|
||||
Q <= D;
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
//-----------------------------
|
||||
// D-type flip-flop with active-high asynchronous set
|
||||
//-----------------------------
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module dffs(
|
||||
output reg Q,
|
||||
input D,
|
||||
input S,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
initial Q = INIT;
|
||||
case(|IS_C_INVERTED)
|
||||
1'b0:
|
||||
always @(posedge C or posedge S)
|
||||
if (S == 1'b1)
|
||||
Q <= 1'b1;
|
||||
else
|
||||
Q <= D;
|
||||
1'b1:
|
||||
always @(negedge C or posedge S)
|
||||
if (S == 1'b1)
|
||||
Q <= 1'b1;
|
||||
else
|
||||
Q <= D;
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
//-----------------------------
|
||||
// D-type flip-flop with active-low asynchronous reset
|
||||
//-----------------------------
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module dffrn(
|
||||
output reg Q,
|
||||
input D,
|
||||
input RN,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
initial Q = INIT;
|
||||
case(|IS_C_INVERTED)
|
||||
1'b0:
|
||||
always @(posedge C or negedge RN)
|
||||
if (RN == 1'b0)
|
||||
Q <= 1'b0;
|
||||
else
|
||||
Q <= D;
|
||||
1'b1:
|
||||
always @(negedge C or negedge RN)
|
||||
if (RN == 1'b0)
|
||||
Q <= 1'b0;
|
||||
else
|
||||
Q <= D;
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
//-----------------------------
|
||||
// D-type flip-flop with active-low asynchronous set
|
||||
//-----------------------------
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module dffsn(
|
||||
output reg Q,
|
||||
input D,
|
||||
input SN,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
initial Q = INIT;
|
||||
case(|IS_C_INVERTED)
|
||||
1'b0:
|
||||
always @(posedge C or negedge SN)
|
||||
if (SN == 1'b0)
|
||||
Q <= 1'b1;
|
||||
else
|
||||
Q <= D;
|
||||
1'b1:
|
||||
always @(negedge C or negedge SN)
|
||||
if (SN == 1'b0)
|
||||
Q <= 1'b1;
|
||||
else
|
||||
Q <= D;
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
// Basic DFF
|
||||
module \$_DFF_P_ (D, C, Q);
|
||||
input D;
|
||||
input C;
|
||||
output Q;
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
|
||||
endmodule
|
||||
|
||||
// Async active-high reset
|
||||
module \$_DFF_PP0_ (D, C, R, Q);
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
output Q;
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
|
||||
endmodule
|
||||
|
||||
// Async active-high set
|
||||
module \$_DFF_PP1_ (D, C, R, Q);
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
output Q;
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
|
||||
endmodule
|
||||
|
||||
// Async active-low reset
|
||||
module \$_DFF_PN0_ (D, C, R, Q);
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
output Q;
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
|
||||
endmodule
|
||||
|
||||
// Async active-low set
|
||||
module \$_DFF_PN1_ (D, C, R, Q);
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
output Q;
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
|
||||
endmodule
|
||||
|
|
@ -93,4 +93,4 @@ module latchre (
|
|||
if (S) Q <= 1'b1;
|
||||
else if (E && G) Q <= D;
|
||||
end
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -10,3 +10,4 @@ echo -e "IWLS'05 benchmark regression tests";
|
|||
run-task benchmark_sweep/iwls2005 --debug --show_thread_logs
|
||||
# Run a quick but relaxed QoR check for heterogeneous blocks
|
||||
#python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv --check_tolerance 0.2,100
|
||||
python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/config/metric_checklist.csv --check_tolerance 0.2,100
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
mult_blocks,total_routing_area,total_routing_time,TotalRunTime,packing_time,name,io_blocks,memory_blocks,placement_time,average_net_length,routing_time,clb_blocks,critical_path,total_wire_length,total_logic_block_area
|
||||
0,8.02931,3.53,143,85.87,00_eth_top_MIN_ROUTE_CHAN_WIDTH,211,4,6.78,15.2037,3.53,292,4.34288e-09,36945,1
|
||||
0,7.23279,3.54,108,53.90,00_mc_top_MIN_ROUTE_CHAN_WIDTH,267,0,5.49,17.0883,3.54,254,7.331640000000001e-09,35800,1
|
||||
0,620306.,0.17,14,10.78,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.33,7.10949,0.17,18,2.56241e-09,974,970092
|
||||
0,5.94202,3.04,85,34.23,00_tv80s_MIN_ROUTE_CHAN_WIDTH,46,0,3.71,19.8659,3.04,202,8.90858e-09,32600,1
|
||||
0,1.13704,5.56,211,139.55,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,196,11,10.12,16.2042,5.56,414,3.8128200000000005e-09,63472,2
|
||||
0,7.23279,2.87,338,31.76,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,388,0,6.09,14.2891,2.87,267,4.37135e-09,30993,1
|
||||
0,9.51115,4.49,274,51.71,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,389,16,7.55,15.5093,4.49,343,4.749290000000001e-09,40898,2
|
||||
1,1.13704,6.18,431,91.44,00_fpu_MIN_ROUTE_CHAN_WIDTH,110,0,8.42,14.6717,6.18,429,1.6591900000000002e-07,58012,2
|
||||
0,1.13704,5.7,275,201.24,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,367,0,11.01,14.4637,5.70,424,4.54535e-09,64002,2
|
||||
0,2.10319,0.84,25,11.70,00_spi_top_MIN_ROUTE_CHAN_WIDTH,90,0,1.25,14.5174,0.84,69,5.46323e-09,7941,3
|
||||
0,4.62242,1.97,60,29.06,00_aes_MIN_ROUTE_CHAN_WIDTH,389,0,3.77,15.9033,1.97,151,5.37676e-09,21883,8
|
||||
0,8.86284,4.28,199,139.64,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,235,0,6.63,17.6241,4.28,305,5.084290000000001e-09,48290,1
|
||||
0,1.21212,86.15,694,97.52,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,2546,0,64.43,42.0125,86.15,831,5.21772e-09,258839,4
|
||||
0,789582.,0.3,10,5.62,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,33,0,0.41,7.73636,0.30,23,3.07388e-09,1702,1
|
||||
0,620306.,0.16,8,4.79,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.24,6.14844,0.16,17,1.77641e-09,787,916198
|
||||
0,417802.,0.1,4,2.35,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.14,5.20548,0.10,9,1.68994e-09,380,485046
|
||||
0,1.43501,0.49,42,31.70,00_des_MIN_ROUTE_CHAN_WIDTH,189,0,0.84,9.10709,0.49,43,3.6623500000000003e-09,5783,2
|
||||
0,620306.,0.15,6,2.75,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,33,0,0.21,6.56044,0.15,13,1.75847e-09,597,700622
|
||||
0,3.94926,1.45,78,31.64,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,431,0,2.89,13.4492,1.45,85,4.274350000000001e-09,14041,4
|
||||
|
|
|
@ -0,0 +1,6 @@
|
|||
##########################################################
|
||||
# Metrics to check for IWLS benchmark bitstream generation
|
||||
##########################################################
|
||||
metric
|
||||
mult_blocks
|
||||
memory_blocks
|
||||
|
|
|
@ -17,10 +17,11 @@ fpga_flow=yosys_vpr
|
|||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
|
||||
# Yosys script parameters
|
||||
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v
|
||||
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v
|
||||
yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v
|
||||
yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt
|
||||
yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
|
||||
yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v
|
||||
|
|
@ -30,48 +31,43 @@ yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINW
|
|||
vpr_route_chan_width=300
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
# RTL netlists from IWLS 2005 benchmark release
|
||||
# Comment out due to DFF synthesis problems
|
||||
# Comment out it requires falling edge latches which are not supported yet
|
||||
#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/*.v
|
||||
#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/*.v
|
||||
#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/*.v
|
||||
#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/simple_spi/rtl/*.v
|
||||
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/*.v
|
||||
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/*.v
|
||||
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/simple_spi/rtl/*.v
|
||||
# Comment out due to VHDL is not supported by Yosys without Verific
|
||||
#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/steppermotordrive/rtl/*.vhd
|
||||
bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/tv80/rtl/*.v
|
||||
# Comment out due to DFF synthesis problems
|
||||
#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/*.v
|
||||
bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/*.v
|
||||
# AES core has two top modules that can be tested: encryption and decryption
|
||||
# Synthesis is too long; skip it
|
||||
#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v
|
||||
#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v
|
||||
#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/fpu/rtl/*.v
|
||||
# Comment out due to DFF synthesis problems
|
||||
#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/pci/rtl/*.v
|
||||
#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/spi/rtl/*.v
|
||||
#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/*.v
|
||||
bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v
|
||||
bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v
|
||||
bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/fpu/rtl/*.v
|
||||
bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/pci/rtl/*.v
|
||||
bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/spi/rtl/*.v
|
||||
bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/*.v
|
||||
bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/*.v
|
||||
# Comment out due to DFF synthesis problems
|
||||
#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/*.v
|
||||
bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/*.v
|
||||
## DES has two versions: area-optimized and performance optimized
|
||||
bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/*.v
|
||||
bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/*.v
|
||||
# Comment out due to DFF synthesis problems
|
||||
#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/i2c/rtl/*.v
|
||||
# Comment out due to DFF synthesis problems
|
||||
#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/sasc/rtl/*.v
|
||||
# The DES has same top-level module name as systemcdes
|
||||
# Currently openfpga flow has a bug which does not allow same top-level module name
|
||||
#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/*.v
|
||||
#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/*.v
|
||||
bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/i2c/rtl/*.v
|
||||
bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/sasc/rtl/*.v
|
||||
bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ss_pcm/rtl/*.v
|
||||
# Comment out due to DFF synthesis problems
|
||||
#bench20=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/*.v
|
||||
bench20=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/*.v
|
||||
bench21=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/*.v
|
||||
# Comment out due to DFF synthesis problems
|
||||
#bench22=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/*.v
|
||||
bench22=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/*.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
|
||||
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
|
||||
bench0_top = ac97_top
|
||||
bench1_top = eth_top
|
||||
bench2_top = mc_top
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue