diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index 358ae2fb9..74bb744f0 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -96,20 +96,49 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct /* Find the net mapped to this pin in clustering results*/ ClusterNetId cluster_net_id = clustering_ctx.clb_nlist.block_net(blk_id, j); - /* Ignore those net have never been routed */ + /* Ignore those net have never been routed: this check is valid only + * when both packer has mapped a net to the pin and the router leaves the pin to be unmapped + * This is important because we cannot bypass when router forces a valid net to be mapped + * and the net remapping has to be considered + */ if ( (ClusterNetId::INVALID() != cluster_net_id) + && (ClusterNetId::INVALID() == routing_net_id) && (true == clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id))) { + VTR_LOGV(verbose, + "Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' as it is not routed\n", + clustering_ctx.clb_nlist.block_pb(blk_id)->name, + grid_coord.x(), grid_coord.y(), + clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number + ); continue; } /* Ignore used in local cluster only, reserved one CLB pin */ if ( (ClusterNetId::INVALID() != cluster_net_id) && (0 == clustering_ctx.clb_nlist.net_sinks(cluster_net_id).size())) { + VTR_LOGV(verbose, + "Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' as it is a local net inside the cluster\n", + clustering_ctx.clb_nlist.block_pb(blk_id)->name, + grid_coord.x(), grid_coord.y(), + clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number + ); continue; } /* If matched, we finish here */ if (routing_net_id == cluster_net_id) { + VTR_LOGV(verbose, + "Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' as it matches cluster routing\n", + clustering_ctx.clb_nlist.block_pb(blk_id)->name, + grid_coord.x(), grid_coord.y(), + clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number + ); continue; } diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys new file mode 100644 index 000000000..7244532e5 --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys @@ -0,0 +1,105 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +${READ_VERILOG_FILE} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt + +opt_expr +opt_clean +check +opt +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################## +# Map multipliers +# Inspired from synth_xilinx.cc +######################### +# Avoid merging any registers into DSP, reserve memory port registers first +memory_dff +wreduce t:$mul +techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} +select a:mul2dsp +setattr -unset mul2dsp +opt_expr -fine +wreduce +select -clear +chtype -set $mul t:$__soft_mul# Extract arithmetic functions + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +techmap +alumacc +share +opt +fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +opt -fast +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map logics to BRAMs +######################### +memory_bram -rules ${YOSYS_BRAM_MAP_RULES} +techmap -map ${YOSYS_BRAM_MAP_VERILOG} +opt -fast -mux_undef -undriven -fine +memory_map +opt -undriven -fine + +######################### +# Map flip-flops +######################### +techmap -map ${YOSYS_DFF_MAP_VERILOG} +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_rmdff +opt_clean +opt + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml new file mode 100644 index 000000000..d1cf24921 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml @@ -0,0 +1,333 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v index a0548c54c..a1d3e2407 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dff.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v @@ -289,6 +289,34 @@ assign Q = q_reg; endmodule //End Of Module +//----------------------------------------------------- +// Function : A multi-functional D-type flip-flop with +// - asynchronous reset +// which can be switched between active-low and active hight +// - asynchronous set which can be switched +// which can be switched between active-low and active hight +//----------------------------------------------------- +module MULTI_MODE_DFFSRQ ( + input SET, // Set input + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity +); + +wire post_set = mode ? ~SET : SET; +wire post_reset = mode ? ~RST : RST; + +DFFSRQ FF_CORE (.SET(post_set), + .RST(post_rst), + .CK(CK), + .D(D), + .Q(Q) + ); + +endmodule //End Of Module + //----------------------------------------------------- // Function : D-type flip-flop with // - asynchronous active high reset diff --git a/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga index 04089a450..49f1aac73 100644 --- a/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga @@ -1,8 +1,8 @@ # Run VPR for the 'and' design # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # This is due to the Fc_in of clock port is set to 0 for global wiring -#--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} +# The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v new file mode 100644 index 000000000..cc64801a3 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v @@ -0,0 +1,220 @@ +//----------------------------- +// Dual-port RAM 1024x8 bit (8Kbit) +// Core logic +//----------------------------- +module dpram_1024x8_core ( + input wclk, + input wen, + input [0:9] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:9] raddr, + output [0:7] data_out ); + + reg [0:7] ram[0:1023]; + reg [0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule + +//----------------------------- +// Dual-port RAM 1024x8 bit (8Kbit) wrapper +// where the read clock and write clock +// are combined to a unified clock +//----------------------------- +module dpram_1024x8 ( + input clk, + input wen, + input ren, + input [0:9] waddr, + input [0:9] raddr, + input [0:7] data_in, + output [0:7] data_out ); + + dpram_1024x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + +//----------------------------- +// 36-bit multiplier +//----------------------------- +module mult_36( + input [0:35] A, + input [0:35] B, + output [0:71] Y +); + +assign Y = A * B; + +endmodule + +//----------------------------- +// Native D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v new file mode 100644 index 000000000..f8eed8db0 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v @@ -0,0 +1,48 @@ +// Basic DFF +module \$_DFF_P_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Async active-high reset +module \$_DFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Async active-high set +module \$_DFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Async active-low set +module \$_DFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v index 90926cef6..d4798a906 100644 --- a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v @@ -93,4 +93,4 @@ module latchre ( if (S) Q <= 1'b1; else if (E && G) Q <= D; end -endmodule \ No newline at end of file +endmodule diff --git a/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh index 6bbb44633..1c00bd150 100755 --- a/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh @@ -10,3 +10,4 @@ echo -e "IWLS'05 benchmark regression tests"; run-task benchmark_sweep/iwls2005 --debug --show_thread_logs # Run a quick but relaxed QoR check for heterogeneous blocks #python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv --check_tolerance 0.2,100 +python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/config/metric_checklist.csv --check_tolerance 0.2,100 diff --git a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv new file mode 100644 index 000000000..fe07fa1c1 --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv @@ -0,0 +1,20 @@ +mult_blocks,total_routing_area,total_routing_time,TotalRunTime,packing_time,name,io_blocks,memory_blocks,placement_time,average_net_length,routing_time,clb_blocks,critical_path,total_wire_length,total_logic_block_area +0,8.02931,3.53,143,85.87,00_eth_top_MIN_ROUTE_CHAN_WIDTH,211,4,6.78,15.2037,3.53,292,4.34288e-09,36945,1 +0,7.23279,3.54,108,53.90,00_mc_top_MIN_ROUTE_CHAN_WIDTH,267,0,5.49,17.0883,3.54,254,7.331640000000001e-09,35800,1 +0,620306.,0.17,14,10.78,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.33,7.10949,0.17,18,2.56241e-09,974,970092 +0,5.94202,3.04,85,34.23,00_tv80s_MIN_ROUTE_CHAN_WIDTH,46,0,3.71,19.8659,3.04,202,8.90858e-09,32600,1 +0,1.13704,5.56,211,139.55,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,196,11,10.12,16.2042,5.56,414,3.8128200000000005e-09,63472,2 +0,7.23279,2.87,338,31.76,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,388,0,6.09,14.2891,2.87,267,4.37135e-09,30993,1 +0,9.51115,4.49,274,51.71,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,389,16,7.55,15.5093,4.49,343,4.749290000000001e-09,40898,2 +1,1.13704,6.18,431,91.44,00_fpu_MIN_ROUTE_CHAN_WIDTH,110,0,8.42,14.6717,6.18,429,1.6591900000000002e-07,58012,2 +0,1.13704,5.7,275,201.24,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,367,0,11.01,14.4637,5.70,424,4.54535e-09,64002,2 +0,2.10319,0.84,25,11.70,00_spi_top_MIN_ROUTE_CHAN_WIDTH,90,0,1.25,14.5174,0.84,69,5.46323e-09,7941,3 +0,4.62242,1.97,60,29.06,00_aes_MIN_ROUTE_CHAN_WIDTH,389,0,3.77,15.9033,1.97,151,5.37676e-09,21883,8 +0,8.86284,4.28,199,139.64,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,235,0,6.63,17.6241,4.28,305,5.084290000000001e-09,48290,1 +0,1.21212,86.15,694,97.52,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,2546,0,64.43,42.0125,86.15,831,5.21772e-09,258839,4 +0,789582.,0.3,10,5.62,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,33,0,0.41,7.73636,0.30,23,3.07388e-09,1702,1 +0,620306.,0.16,8,4.79,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.24,6.14844,0.16,17,1.77641e-09,787,916198 +0,417802.,0.1,4,2.35,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.14,5.20548,0.10,9,1.68994e-09,380,485046 +0,1.43501,0.49,42,31.70,00_des_MIN_ROUTE_CHAN_WIDTH,189,0,0.84,9.10709,0.49,43,3.6623500000000003e-09,5783,2 +0,620306.,0.15,6,2.75,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,33,0,0.21,6.56044,0.15,13,1.75847e-09,597,700622 +0,3.94926,1.45,78,31.64,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,431,0,2.89,13.4492,1.45,85,4.274350000000001e-09,14041,4 diff --git a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/metric_checklist.csv b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/metric_checklist.csv new file mode 100644 index 000000000..2adc74073 --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/metric_checklist.csv @@ -0,0 +1,6 @@ +########################################################## +# Metrics to check for IWLS benchmark bitstream generation +########################################################## +metric +mult_blocks +memory_blocks diff --git a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf index 60eaeec4a..79929256d 100644 --- a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf @@ -17,10 +17,11 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml # Yosys script parameters -yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v @@ -30,48 +31,43 @@ yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINW vpr_route_chan_width=300 [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml [BENCHMARKS] # RTL netlists from IWLS 2005 benchmark release -# Comment out due to DFF synthesis problems +# Comment out it requires falling edge latches which are not supported yet #bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/*.v -#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/*.v -#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/*.v -#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/simple_spi/rtl/*.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/*.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/*.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/simple_spi/rtl/*.v # Comment out due to VHDL is not supported by Yosys without Verific #bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/steppermotordrive/rtl/*.vhd bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/tv80/rtl/*.v -# Comment out due to DFF synthesis problems -#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/*.v +bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/*.v # AES core has two top modules that can be tested: encryption and decryption # Synthesis is too long; skip it -#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v -#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v -#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/fpu/rtl/*.v -# Comment out due to DFF synthesis problems -#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/pci/rtl/*.v -#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/spi/rtl/*.v -#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/*.v +bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v +bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v +bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/fpu/rtl/*.v +bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/pci/rtl/*.v +bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/spi/rtl/*.v +bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/*.v bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/*.v -# Comment out due to DFF synthesis problems -#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/*.v +bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/*.v ## DES has two versions: area-optimized and performance optimized -bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/*.v -bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/*.v -# Comment out due to DFF synthesis problems -#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/i2c/rtl/*.v -# Comment out due to DFF synthesis problems -#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/sasc/rtl/*.v +# The DES has same top-level module name as systemcdes +# Currently openfpga flow has a bug which does not allow same top-level module name +#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/*.v +#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/*.v +bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/i2c/rtl/*.v +bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/sasc/rtl/*.v bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ss_pcm/rtl/*.v -# Comment out due to DFF synthesis problems -#bench20=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/*.v +bench20=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/*.v bench21=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/*.v -# Comment out due to DFF synthesis problems -#bench22=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/*.v +bench22=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/*.v [SYNTHESIS_PARAM] -bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys bench0_top = ac97_top bench1_top = eth_top bench2_top = mc_top diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml new file mode 100644 index 000000000..db1b5bef4 --- /dev/null +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml @@ -0,0 +1,1223 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + clb.clk clb.reset clb.set + clb.cin + clb.O[9:0] clb.I[19:0] + clb.cout clb.O[19:10] clb.I[39:20] + + + + + + + + + + + + + + + + + + + memory.clk + + memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0] + memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4] + + + + + + + + + + + + + + mult_36.b[0:9] mult_36.b[10:35] mult_36.out[36:71] + + mult_36.a[0:9] mult_36.a[10:35] mult_36.out[0:35] + + + + + + + + + + + + + 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