From cbb7d41b6e0934d6e3871426ef983dedeaa196b0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 23 Apr 2021 14:15:13 -0600
Subject: [PATCH] [Script] Enable constant net routing for VTR benchmarks

---
 .../vtr_benchmark_example_script.openfpga                     | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga
index 04089a450..49f1aac73 100644
--- a/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga
@@ -1,8 +1,8 @@
 # Run VPR for the 'and' design
 # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
 # This is due to the Fc_in of clock port is set to 0 for global wiring
-#--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH}
+# The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}