Andrew Pond
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8f18a9ad9a
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added complete bram sizing files
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2022-02-07 12:19:31 -07:00 |
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Andrew Pond
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8c38747d6c
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revised PR
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2021-12-16 09:53:16 -07:00 |
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Andrew Pond
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727a2ac771
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added 4K bram
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2021-12-16 09:05:06 -07:00 |
|
Andrew Pond
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dd983ec348
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CLB carry issue
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2021-11-11 12:11:42 -07:00 |
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Andrew Pond
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42d5c1403a
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adder chain arch working
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2021-11-10 16:20:31 -07:00 |
|
Andrew Pond
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7f31f527a4
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16 bit adder chain working
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2021-10-21 09:55:57 -06:00 |
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Andrew Pond
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a486c2690f
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Merge branch 'timing_annotation' into arch_exploration
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2021-09-28 16:22:13 -06:00 |
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Andrew Pond
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cebcdba4d4
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added fpgatoolperf vexriscv src
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2021-09-28 13:32:41 -06:00 |
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Andrew Pond
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0783072be7
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fixed errors
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2021-08-16 16:12:51 -06:00 |
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Andrew Pond
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73854bbe66
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bram timing update
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2021-07-29 12:32:52 -06:00 |
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Andrew Pond
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cb0dbd6f2f
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responding to Xifan's comments in PR
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2021-07-26 17:40:34 -06:00 |
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Andrew Pond
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e39e9b8c26
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finishing touches for PR
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2021-07-23 12:08:32 -06:00 |
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Andrew Pond
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ce71466b32
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fixed bram CI error
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2021-07-23 11:16:26 -06:00 |
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Andrew Pond
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05c4a253cc
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fixed CI errors
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2021-07-22 16:39:44 -06:00 |
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Andrew Pond
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29f67479cc
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yosys techlib directory restructure
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2021-07-22 15:14:14 -06:00 |
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Andrew Pond
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6cb51d1e7d
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timing files renamed
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2021-07-21 14:12:32 -06:00 |
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Andrew Pond
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60ac09d315
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removed duplicate yosys script
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2021-07-21 08:09:20 -06:00 |
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Andrew Pond
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805053f4be
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created timing annotation file
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2021-07-20 11:45:35 -06:00 |
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Andrew Pond
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afea5bb44c
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started updating timings
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2021-07-19 10:48:55 -06:00 |
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Andrew Pond
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a9755c4dec
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started modifying arch files
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2021-07-16 09:09:25 -06:00 |
Andrew Pond
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b3870b3107
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Merge branch 'master' into bram_changes
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2021-07-06 15:33:40 -06:00 |
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Andrew Pond
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6445507ddf
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pmux2mux yosys script change
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2021-07-06 14:19:28 -06:00 |
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Andrew Pond
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1409b3e855
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pmux2mux.v path change
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2021-07-06 12:25:51 -06:00 |
tangxifan
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223e06d23c
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Merge pull request #359 from lnis-uofu/pin_constraint_polarity
Add Test Cases for the Signal Polarity Support in Pin Constraint Files
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2021-07-02 18:51:24 -06:00 |
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tangxifan
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9f03ecb160
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[Test] Patch test case due to the changes in counter benchmarks
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2021-07-02 17:57:39 -06:00 |
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tangxifan
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64dcdaec61
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[Test] Update all the tasks that use counter benchmark
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2021-07-02 17:29:13 -06:00 |
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tangxifan
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5a6874e9f1
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[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks
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2021-07-02 17:28:17 -06:00 |
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tangxifan
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8baf60603a
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[Script] Patching the run_fpga_task.py on pin constraint files
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2021-07-02 15:59:29 -06:00 |
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tangxifan
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e9d29e27e5
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[Tool] Bug fix
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2021-07-02 15:32:30 -06:00 |
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tangxifan
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fdf94cba83
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
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2021-07-02 15:28:34 -06:00 |
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tangxifan
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3cbe266c44
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[Test] Bug fix on the test case for multi-mode FF and pin constraints
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2021-07-02 15:27:27 -06:00 |
Ganesh Gore
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c67807868c
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[bugFix] Benchamrk variable declaration
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2021-07-02 15:26:39 -06:00 |
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tangxifan
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6e6c3e9fa4
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[Tool] Patch the critical bug in the use of signal polarity in pin constraints
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2021-07-02 15:26:21 -06:00 |
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tangxifan
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3aacce2a96
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Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
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2021-07-02 14:04:42 -06:00 |
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tangxifan
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a5101be2f6
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
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2021-07-02 13:58:33 -06:00 |
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tangxifan
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2214575a0a
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Merge pull request #358 from lnis-uofu/ganesh_dev
Testcase for benchmark specific variables
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2021-07-02 13:54:07 -06:00 |
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Ganesh Gore
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edd5be2cae
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[CI] Added testcase for benchmark variable
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2021-07-02 12:51:34 -06:00 |
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tangxifan
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dcb89cb16b
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[Arch] Patch architecture due to missing mode bit definition
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2021-07-02 11:41:29 -06:00 |
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tangxifan
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5286f9ba25
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[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
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2021-07-02 11:39:00 -06:00 |
ganeshgore
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b8bed59ecf
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Merge pull request #356 from lnis-uofu/pin_constraint_polarity
[WIP] Support custom default value in Pin Constraint File
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2021-07-02 10:20:20 -07:00 |
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tangxifan
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02fd2a69b3
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[Script] Add dff with active-low async reset to default yosys tech lib
|
2021-07-02 11:17:43 -06:00 |
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tangxifan
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477e535344
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[HDL] Added a multi-mode FF design with configurable asynchronous reset
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2021-07-02 11:13:03 -06:00 |
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tangxifan
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fd85f956c9
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[Arch] Update k4n4 arch with true multi-mode flip-flop
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2021-07-02 11:08:39 -06:00 |
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tangxifan
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0b6a9b06f5
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[Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality
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2021-07-02 10:39:07 -06:00 |
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tangxifan
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3906497ef5
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
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2021-07-02 10:27:40 -06:00 |
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tangxifan
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f8fb056a42
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Merge branch 'master' into pin_constraint_polarity
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2021-07-02 10:05:17 -06:00 |
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tangxifan
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e79da64e95
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Merge pull request #354 from lnis-uofu/ganesh_dev
[Flow] Allows benchmark specific Variable declaration
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2021-07-02 10:05:03 -06:00 |
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tangxifan
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43afaca17c
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[Doc] Add more details about the new syntax
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2021-07-01 23:51:54 -06:00 |
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tangxifan
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0851075bc9
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[Doc] Update documentation about the new feature in pin constraint file
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2021-07-01 23:47:36 -06:00 |
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tangxifan
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9074bffa68
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[Tool] Support customized default value in pin constraint file
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2021-07-01 23:43:19 -06:00 |