riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

CLB carry issue

This commit is contained in:
Andrew Pond 2021-11-11 12:11:42 -07:00
parent 42d5c1403a
commit dd983ec348
2 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
View File

@ -51,6 +51,12 @@ wreduce
select -clear
chtype -set $mul t:$__soft_mul# Extract arithmetic functions
#########################
# Map $alu to carry chain
#########################
alumacc
techmap -map ${YOSYS_ADDER_MAP_VERILOG}
#########################
# Run coarse synthesis
#########################

12
openfpga_flow/openfpga_timing_annotation/design_variables.yml
View File

@ -46,6 +46,18 @@ MULT18_LR_B2B_DELAY_MAX: 1.46e-9
MULT18_LR_B2B_DELAY_MIN: 1.46e-9
################# Adder Delays #################
ADDER_CIN2OUT_DELAY: 1.21e-9
ADDER_CIN2COUT_DELAY: 1.21e-9
ADDER_IN2OUT_DELAY: 1.21e-9
ADDER_IN2COUT_DELAY: 1.21e-9
ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
################# BRAM Delays #################
DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12