diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
index d0ff395b6..4111e11d8 100644
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
@@ -51,6 +51,12 @@ wreduce
 select -clear
 chtype -set $mul t:$__soft_mul# Extract arithmetic functions
 
+#########################
+# Map $alu to carry chain
+#########################
+alumacc
+techmap -map ${YOSYS_ADDER_MAP_VERILOG}
+
 #########################
 # Run coarse synthesis
 #########################
diff --git a/openfpga_flow/openfpga_timing_annotation/design_variables.yml b/openfpga_flow/openfpga_timing_annotation/design_variables.yml
index ca9d82179..36a092e3d 100644
--- a/openfpga_flow/openfpga_timing_annotation/design_variables.yml
+++ b/openfpga_flow/openfpga_timing_annotation/design_variables.yml
@@ -46,6 +46,18 @@ MULT18_LR_B2B_DELAY_MAX: 1.46e-9
 MULT18_LR_B2B_DELAY_MIN: 1.46e-9
 
 
+################# Adder Delays #################
+
+ADDER_CIN2OUT_DELAY: 1.21e-9
+ADDER_CIN2COUT_DELAY: 1.21e-9
+ADDER_IN2OUT_DELAY: 1.21e-9
+ADDER_IN2COUT_DELAY: 1.21e-9
+
+ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
+ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
+
+
+
 ################# BRAM Delays #################
 
 DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12