revised PR
This commit is contained in:
Andrew Pond
parent
727a2ac771
commit
8c38747d6c
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@ -1,7 +1,7 @@
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// Creating a scaleable adder
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module adder_16(cout, sum, a, b, cin);
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parameter size = 3; /* declare a parameter. default required */
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parameter size = 16; /* declare a parameter. default required */
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output cout;
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output [size-1:0] sum; // sum uses the size parameter
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input cin;
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@ -1,39 +0,0 @@
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// Creating a scaleable adder
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module adder_16_clk #(
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parameter size = 2
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)(
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output reg cout,
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output reg [size-1:0] sum, // sum uses the size parameter
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input cin,
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input [size-1:0] a, b, // 'a' and 'b' use the size parameter
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input clk_in,
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input rst
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);
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// reg [size-1:0] _sum;
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// reg _cout;
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always @(posedge clk_in) begin
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if (rst)
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{sum,cout} <= 0;
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else
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{sum,cout} <= a + b + cin;
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end
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// assign sum = _sum;
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// assign cout = _cout;
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// assign {cout, sum} = a + b + cin;
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endmodule
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@ -1,41 +0,0 @@
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module adder_16_wrapper(
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output cout,
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output sum_0,
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output sum_1,
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output sum_2,
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output sum_3,
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input cin,
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input a_0,
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input a_1,
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input a_2,
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input a_3,
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input b_0,
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input b_1,
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input b_2,
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input b_3
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);
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wire [4:0] sum;
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assign sum_0 = sum[0];
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assign sum_1 = sum[1];
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assign sum_2 = sum[2];
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assign sum_3 = sum[3];
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wire [4:0] a;
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assign a_0 = a[0];
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assign a_1 = a[1];
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assign a_2 = a[2];
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assign a_3 = a[3];
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wire [4:0] b;
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assign b_0 = b[0];
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assign b_1 = b[1];
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assign b_2 = b[2];
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assign b_3 = b[3];
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adder_16 DUT(
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.cout(cout),
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.sum(sum),
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.cin(cin),
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.a(a),
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.b(b) );
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endmodule
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File diff suppressed because it is too large
Load Diff
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@ -1,352 +0,0 @@
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k4_frac_cc_sky130nm.xml
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- General purpose logic block
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- K = 4, N = 8, I = 24
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- Routing architecture
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- 10% L = 1, fc_in = 0.15, Fc_out = 0.10
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- 10% L = 2, fc_in = 0.15, Fc_out = 0.10
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- 80% L = 4, fc_in = 0.15, Fc_out = 0.10
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- DSP block:
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- Multi-mode multiplier which can operate in two modes
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- Mode A: 18-bit multiplier
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- Mode B: two independent 9-bit multipliers
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- Skywater 130nm PDK
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- circuit models are binded to the opensource skywater
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foundry high-density standard cell library
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<!-- Dummy Circuit model -->
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<circuit_model type="inv_buf" name="inv_01" prefix="inv_01" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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</circuit_model>
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<!-- Dummy Circuit model -->
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<circuit_model type="inv_buf" name="inv_02" prefix="inv_02" verilog_netlist="./SRC/CustomModules/sky130_fd_sc_hd_wrapper.v">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
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<design_technology type="cmos" topology="buffer" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
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<design_technology type="cmos" topology="OR"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" lib_name="A" size="1"/>
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<port type="input" prefix="b" lib_name="B" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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<delay_matrix type="rise" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<!-- Define a circuit model for the standard cell MUX2
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OpenFPGA requires the following truth table for the MUX2
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When the select signal sel is enabled, the first input, i.e., in0
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will be propagated to the output, i.e., out
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If your standard cell provider does not offer the exact truth table,
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you can simply swap the inputs as shown in the example below
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-->
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<circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
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<design_technology type="cmos" topology="MUX2"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in0" lib_name="A1" size="1"/>
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<port type="input" prefix="in1" lib_name="A0" size="1"/>
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<port type="input" prefix="sel" lib_name="S" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
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<!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/>
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<!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="false"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
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<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="sofa_plus_dff" prefix="sofa_plus_dff" verilog_netlist="./SRC/CustomModules/sofa_plus_dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="DI" size="1"/>
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<port type="input" prefix="Test_en" size="1" is_global="true" default_val="0"/>
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<port type="input" prefix="R" size="1" default_val="0"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="C" size="1" default_val="0" />
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<port type="sram" prefix="MODE_SEL" size="2" mode_select="true" circuit_model_name="sofa_plus_ccff" default_val="0"/>
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</circuit_model>
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<circuit_model type="lut" name="frac_lut4_arith" prefix="frac_lut4_arith" dump_structural_verilog="true" verilog_netlist="./SRC/CustomModules/frac_lut4_arith.v">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="false"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
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<lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
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<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
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<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
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<port type="input" prefix="cin" size="1" is_harden_lut_port="true"/>
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<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
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<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
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<port type="output" prefix="cout" size="1" is_harden_lut_port="true"/>
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<port type="sram" prefix="sram" size="16"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sofa_plus_ccff" default_val="1"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="sofa_plus_ccff" prefix="sofa_plus_ccff" verilog_netlist="./SRC/CustomModules/sofa_plus_ccff.v">
|
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
|
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<output_buffer exist="false"/>
|
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="scan_data_in" lib_name="SI" size="1"/>
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<!-- This port allows readback configurable memories without modifying the storage -->
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<!-- <port type="input" prefix="config_readback" lib_name="SCE" size="1" is_global="true" default_val="0"/> -->
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<!-- This port allows programming circuitry is be isolated from datapath logic during programming -->
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<port type="input" prefix="config_enable" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
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<port type="output" prefix="Q" size="1"/>
|
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<port type="output" prefix="CFGQN" size="1"/>
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<port type="output" prefix="CFGQ" size="1"/>
|
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<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
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<port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="sofa_plus_io" prefix="sofa_plus_io" is_default="true" verilog_netlist="./SRC/CustomModules/sofa_plus_io.v">
|
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<design_technology type="cmos"/>
|
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
|
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
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<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
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<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
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<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
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<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sofa_plus_ccff" default_val="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="frac_mult_18_18" prefix="frac_mult_18_18" is_default="true" verilog_netlist="./SRC/CustomModules/frac_mult_18_18.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="A" lib_name="A" size="18"/>
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<port type="input" prefix="B" lib_name="B" size="18"/>
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<port type="output" prefix="Y" lib_name="Y" size="36"/>
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<port type="sram" prefix="mode" lib_name="MODE" size="1" mode_select="true" circuit_model_name="sofa_plus_ccff" default_val="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dpram1k.v">
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<design_technology type="cmos"/>
|
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="waddr" size="7"/>
|
||||
<port type="input" prefix="raddr" size="7"/>
|
||||
<port type="input" prefix="data_in" size="8"/>
|
||||
<port type="input" prefix="wen" size="1"/>
|
||||
<port type="input" prefix="ren" size="1"/>
|
||||
<port type="output" prefix="data_out" size="8"/>
|
||||
<port type="clock" prefix="clk" size="1"/>
|
||||
</circuit_model>
|
||||
</circuit_library>
|
||||
<configuration_protocol>
|
||||
<organization type="scan_chain" circuit_model_name="sofa_plus_ccff" num_regions="12"/>
|
||||
</configuration_protocol>
|
||||
<connection_block>
|
||||
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
|
||||
</connection_block>
|
||||
<switch_block>
|
||||
<switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
|
||||
<switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
|
||||
<switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
|
||||
</switch_block>
|
||||
<routing_segment>
|
||||
<segment name="L1" circuit_model_name="chan_segment"/>
|
||||
<segment name="L2" circuit_model_name="chan_segment"/>
|
||||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<direct_connection>
|
||||
<direct name="carry_chain" circuit_model_name="direct_interc"/>
|
||||
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
||||
</direct_connection>
|
||||
<tile_annotations>
|
||||
<global_port name="clk" is_clock="true" default_val="0">
|
||||
<tile name="clb" port="clk" x="-1" y="-1"/>
|
||||
<tile name="memory" port="clk"/>
|
||||
</global_port>
|
||||
<global_port name="reset" is_reset="true" default_val="0">
|
||||
<tile name="clb" port="reset" x="-1" y="-1"/>
|
||||
</global_port>
|
||||
</tile_annotations>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
|
||||
<pb_type name="io[physical].iopad" circuit_model_name="sofa_plus_io" mode_bits="1"/>
|
||||
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
|
||||
<!-- physical pb_type binding in complex block CLB -->
|
||||
<!-- physical mode will be the default mode if not specified -->
|
||||
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" circuit_model_name="frac_lut4_arith" mode_bits="00"/>
|
||||
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sofa_plus_dff" mode_bits="00"/>
|
||||
<!-- Binding operating pb_type to physical pb_type -->
|
||||
<!-- Binding operating pb_types in mode 'arithmetic' -->
|
||||
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="11"/>
|
||||
<!-- Binding operating pb_types in mode 'n2_lut3' -->
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="01" physical_pb_type_index_factor="0.5">
|
||||
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:2]"/>
|
||||
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="10">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffs].dffs" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="01">
|
||||
<port name="S" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffsn].dffsn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="11">
|
||||
<port name="SN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<!-- Binding operating pb_types in mode 'ble4' -->
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="00">
|
||||
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:3]"/>
|
||||
<port name="out" physical_mode_port="lut4_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="10" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffs].dffs" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="01" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="S" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffsn].dffsn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="11" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="SN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<!-- End physical pb_type binding in complex block CLB -->
|
||||
|
||||
<!-- physical pb_type binding in complex block dsp -->
|
||||
<pb_type name="mult_18.mult_18_core" physical_mode_name="mult_18x18"/>
|
||||
<!-- Bind the primitive pb_type in the physical mode to a circuit model -->
|
||||
<pb_type name="mult_18.mult_18_core[mult_18x18].mult_18x18_slice.mult_18x18" circuit_model_name="frac_mult_18_18" mode_bits="0"/>
|
||||
<pb_type name="mult_18.mult_18_core[mult_9x9].mult_9x9_slice.mult_9x9" physical_pb_type_name="mult_18.mult_18_core[mult_18x18].mult_18x18_slice.mult_18x18" mode_bits="1" physical_pb_type_index_factor="0">
|
||||
<port name="A" physical_mode_port="A[0:8]" physical_mode_port_rotate_offset="9"/>
|
||||
<port name="B" physical_mode_port="B[0:8]" physical_mode_port_rotate_offset="9"/>
|
||||
<port name="Y" physical_mode_port="Y[0:17]" physical_mode_port_rotate_offset="18"/>
|
||||
</pb_type>
|
||||
|
||||
<!-- physical pb_type binding in complex block memory -->
|
||||
<pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/>
|
||||
<!-- END physical pb_type binding in complex block memory -->
|
||||
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
|
|
@ -1,102 +0,0 @@
|
|||
# Yosys synthesis script for ${TOP_MODULE}
|
||||
|
||||
#########################
|
||||
# Parse input files
|
||||
#########################
|
||||
# Read verilog files
|
||||
${READ_VERILOG_FILE}
|
||||
# Read technology library
|
||||
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
|
||||
|
||||
#########################
|
||||
# Prepare for synthesis
|
||||
#########################
|
||||
# Identify top module from hierarchy
|
||||
hierarchy -check -top ${TOP_MODULE}
|
||||
# - Convert process blocks to AST
|
||||
proc
|
||||
# Flatten all the gates/primitives
|
||||
flatten
|
||||
# Identify tri-state buffers from 'z' signal in AST
|
||||
# with follow-up optimizations to clean up AST
|
||||
tribuf -logic
|
||||
opt_expr
|
||||
opt_clean
|
||||
# demote inout ports to input or output port
|
||||
# with follow-up optimizations to clean up AST
|
||||
deminout
|
||||
opt
|
||||
|
||||
opt_expr
|
||||
opt_clean
|
||||
check
|
||||
opt
|
||||
wreduce -keepdc
|
||||
peepopt
|
||||
pmuxtree
|
||||
opt_clean
|
||||
|
||||
########################
|
||||
# Map multipliers
|
||||
# Inspired from synth_xilinx.cc
|
||||
#########################
|
||||
# Avoid merging any registers into DSP, reserve memory port registers first
|
||||
memory_dff
|
||||
|
||||
#########################
|
||||
# Run coarse synthesis
|
||||
#########################
|
||||
# Run a tech map with default library
|
||||
techmap
|
||||
alumacc
|
||||
share
|
||||
opt
|
||||
fsm
|
||||
# Run a quick follow-up optimization to sweep out unused nets/signals
|
||||
opt -fast
|
||||
# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells
|
||||
memory -nomap
|
||||
opt_clean
|
||||
|
||||
#########################
|
||||
# Map logics to BRAMs
|
||||
#########################
|
||||
memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
|
||||
techmap -map ${YOSYS_BRAM_MAP_VERILOG}
|
||||
opt -fast -mux_undef -undriven -fine
|
||||
memory_map
|
||||
opt -undriven -fine
|
||||
|
||||
#########################
|
||||
# Map pmuxes to muxes
|
||||
#########################
|
||||
techmap -map +/pmux2mux.v
|
||||
|
||||
#########################
|
||||
# Map flip-flops
|
||||
#########################
|
||||
techmap -map ${YOSYS_DFF_MAP_VERILOG}
|
||||
opt_expr -mux_undef
|
||||
simplemap
|
||||
opt_expr
|
||||
opt_merge
|
||||
opt_rmdff
|
||||
opt_clean
|
||||
opt
|
||||
|
||||
#########################
|
||||
# Map LUTs
|
||||
#########################
|
||||
abc -lut ${LUT_SIZE}
|
||||
|
||||
#########################
|
||||
# Check and show statisitics
|
||||
#########################
|
||||
hierarchy -check
|
||||
stat
|
||||
|
||||
#########################
|
||||
# Output netlists
|
||||
#########################
|
||||
opt_clean -purge
|
||||
write_blif ${OUTPUT_BLIF}
|
||||
|
|
@ -1,116 +0,0 @@
|
|||
# Yosys synthesis script for ${TOP_MODULE}
|
||||
|
||||
#########################
|
||||
# Parse input files
|
||||
#########################
|
||||
# Read verilog files
|
||||
${READ_VERILOG_FILE}
|
||||
# Read technology library
|
||||
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
|
||||
|
||||
#########################
|
||||
# Prepare for synthesis
|
||||
#########################
|
||||
# Identify top module from hierarchy
|
||||
hierarchy -check -top ${TOP_MODULE}
|
||||
# - Convert process blocks to AST
|
||||
proc
|
||||
# Flatten all the gates/primitives
|
||||
flatten
|
||||
# Identify tri-state buffers from 'z' signal in AST
|
||||
# with follow-up optimizations to clean up AST
|
||||
tribuf -logic
|
||||
opt_expr
|
||||
opt_clean
|
||||
# demote inout ports to input or output port
|
||||
# with follow-up optimizations to clean up AST
|
||||
deminout
|
||||
opt
|
||||
|
||||
opt_expr
|
||||
opt_clean
|
||||
check
|
||||
opt
|
||||
wreduce -keepdc
|
||||
peepopt
|
||||
pmuxtree
|
||||
opt_clean
|
||||
|
||||
########################
|
||||
# Map multipliers
|
||||
# Inspired from synth_xilinx.cc
|
||||
#########################
|
||||
# Avoid merging any registers into DSP, reserve memory port registers first
|
||||
memory_dff
|
||||
wreduce t:$mul
|
||||
techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS}
|
||||
select a:mul2dsp
|
||||
setattr -unset mul2dsp
|
||||
opt_expr -fine
|
||||
wreduce
|
||||
select -clear
|
||||
chtype -set $mul t:$__soft_mul# Extract arithmetic functions
|
||||
|
||||
#########################
|
||||
# Map $alu to carry chain
|
||||
#########################
|
||||
alumacc
|
||||
techmap -map ${YOSYS_ADDER_MAP_VERILOG}
|
||||
|
||||
#########################
|
||||
# Run coarse synthesis
|
||||
#########################
|
||||
# Run a tech map with default library
|
||||
techmap
|
||||
alumacc
|
||||
share
|
||||
opt
|
||||
fsm
|
||||
# Run a quick follow-up optimization to sweep out unused nets/signals
|
||||
opt -fast
|
||||
# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells
|
||||
memory -nomap
|
||||
opt_clean
|
||||
|
||||
#########################
|
||||
# Map logics to BRAMs
|
||||
#########################
|
||||
memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
|
||||
techmap -map ${YOSYS_BRAM_MAP_VERILOG}
|
||||
opt -fast -mux_undef -undriven -fine
|
||||
memory_map
|
||||
opt -undriven -fine
|
||||
|
||||
#########################
|
||||
# Map muxes to pmuxes
|
||||
#########################
|
||||
techmap -map +/pmux2mux.v
|
||||
|
||||
#########################
|
||||
# Map flip-flops
|
||||
#########################
|
||||
techmap -map +/adff2dff.v
|
||||
opt_expr -mux_undef
|
||||
simplemap
|
||||
opt_expr
|
||||
opt_merge
|
||||
opt_rmdff
|
||||
opt_clean
|
||||
opt
|
||||
|
||||
#########################
|
||||
# Map LUTs
|
||||
#########################
|
||||
abc -lut ${LUT_SIZE}
|
||||
|
||||
#########################
|
||||
# Check and show statisitics
|
||||
#########################
|
||||
hierarchy -check
|
||||
stat
|
||||
|
||||
#########################
|
||||
# Output netlists
|
||||
#########################
|
||||
opt_clean -purge
|
||||
write_blif ${OUTPUT_BLIF}
|
||||
|
|
@ -1,253 +0,0 @@
|
|||
<!-- Architecture annotation for OpenFPGA framework
|
||||
This annotation supports the k6_N10_40nm.xml
|
||||
- General purpose logic block
|
||||
- K = 6, N = 10, I = 40
|
||||
- Single mode
|
||||
- Routing architecture
|
||||
- L = 4, fc_in = 0.15, fc_out = 0.1
|
||||
-->
|
||||
<openfpga_architecture>
|
||||
<technology_library>
|
||||
<device_library>
|
||||
<device_model name="logic" type="transistor">
|
||||
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="0.9" pn_ratio="2"/>
|
||||
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
</device_model>
|
||||
<device_model name="io" type="transistor">
|
||||
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="2.5" pn_ratio="3"/>
|
||||
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
</device_model>
|
||||
</device_library>
|
||||
<variation_library>
|
||||
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
</variation_library>
|
||||
</technology_library>
|
||||
<circuit_library>
|
||||
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
|
||||
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
|
||||
<design_technology type="cmos" topology="OR"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="a" size="1"/>
|
||||
<port type="input" prefix="b" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
|
||||
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" lib_name="A" size="1"/>
|
||||
<port type="input" prefix="sel" lib_name="S" size="1"/>
|
||||
<port type="input" prefix="selb" lib_name="SI" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="Y" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||
</circuit_model>
|
||||
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ff" name="MULTI_MODE_DFFRQ" prefix="MULTI_MODE_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="input" prefix="R" lib_name="RST" size="1" default_val="0"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="C" lib_name="CK" size="1" default_val="0"/>
|
||||
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="0"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" fracturable_lut="true"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
|
||||
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="OR2"/>
|
||||
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
|
||||
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
|
||||
<port type="sram" prefix="sram" size="16"/>
|
||||
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
</circuit_model>
|
||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="output" prefix="QN" size="1"/>
|
||||
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
<port type="input" prefix="outpad" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
</circuit_library>
|
||||
<configuration_protocol>
|
||||
<organization type="scan_chain" circuit_model_name="DFFR"/>
|
||||
</configuration_protocol>
|
||||
<connection_block>
|
||||
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</connection_block>
|
||||
<switch_block>
|
||||
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</switch_block>
|
||||
<routing_segment>
|
||||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<tile_annotations>
|
||||
<global_port name="op_clk" tile_port="clb.clk" is_clock="true" default_val="0">
|
||||
<tile name="clb" port="clk"/>
|
||||
</global_port>
|
||||
<global_port name="op_reset" is_reset="true" default_val="0">
|
||||
<tile name="clb" port="reset"/>
|
||||
</global_port>
|
||||
</tile_annotations>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
|
||||
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
|
||||
<!-- physical pb_type binding in complex block CLB -->
|
||||
<!-- physical mode will be the default mode if not specified -->
|
||||
<pb_type name="clb">
|
||||
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="MULTI_MODE_DFFRQ" mode_bits="0"/>
|
||||
<!-- Binding operating pb_type to physical pb_type -->
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
|
||||
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:2]"/>
|
||||
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
|
||||
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:3]"/>
|
||||
<port name="out" physical_mode_port="lut4_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
|
|
@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
|
|||
|
||||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
# to debug use --verbose options
|
||||
link_openfpga_arch --sort_gsb_chan_node_in_edges
|
||||
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
|
||||
# This is due to the Fc_in of clock port is set to 0 for global wiring
|
||||
# The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --disp on
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
# Run VPR for the 'and' design
|
||||
#--write_rr_graph example_rr_graph.xml
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ${OPENFPGA_CLOCK_MODELING} ${OPENFPGA_VPR_DEVICE_LAYOUT}
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT}
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
|
|
|||
|
|
@ -7,13 +7,13 @@ PYTHON_EXEC=python3.8
|
|||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "Micro benchmark regression tests";
|
||||
# run-task benchmark_sweep/counter --debug --show_thread_logs
|
||||
# run-task benchmark_sweep/mac_units --debug --show_thread_logs
|
||||
run-task benchmark_sweep/counter --debug --show_thread_logs
|
||||
run-task benchmark_sweep/mac_units --debug --show_thread_logs
|
||||
|
||||
# # Verify MCNC big20 benchmark suite with ModelSim
|
||||
# # Please make sure you have ModelSim installed in the environment
|
||||
# # Otherwise, it will fail
|
||||
# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
|
||||
# Verify MCNC big20 benchmark suite with ModelSim
|
||||
# Please make sure you have ModelSim installed in the environment
|
||||
# Otherwise, it will fail
|
||||
run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
|
||||
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
|
||||
|
||||
run-task benchmark_sweep/signal_gen --debug --show_thread_logs
|
||||
|
|
|
|||
|
|
@ -698,7 +698,7 @@ def run_rewrite_verilog():
|
|||
# If there is a template script provided, replace parameters from configuration
|
||||
if not args.ys_rewrite_tmpl:
|
||||
script_cmd = [
|
||||
"read_blif -wideports %s" % args.top_module+".blif",
|
||||
"read_blif %s" % args.top_module+".blif",
|
||||
"write_verilog %s" % args.top_module+"_output_verilog.v"
|
||||
]
|
||||
command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]
|
||||
|
|
|
|||
|
|
@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_
|
|||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=3x2
|
||||
# Yosys script parameters
|
||||
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
|
||||
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_sim.v
|
||||
yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams.txt
|
||||
yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
|
||||
yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_map.v
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
|
||||
|
|
|
|||
|
|
@ -1,15 +1,22 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
# Configuration file for running experiments
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
|
||||
# timeout_each_job is timeout for each job
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = false
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
|
|
@ -17,37 +24,28 @@ fpga_flow=yosys_vpr
|
|||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=
|
||||
openfpga_clock_modeling=ideal
|
||||
openfpga_fast_configuration=
|
||||
|
||||
yosys_adder_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/arith_map.v
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
|
||||
# bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
|
||||
# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
|
||||
# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
|
||||
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
|
||||
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys
|
||||
|
||||
bench0_top = adder_16
|
||||
bench0_top = clock_divider
|
||||
bench0_chan_width = 300
|
||||
|
||||
# bench0_top = clock_divider
|
||||
# bench0_chan_width = 300
|
||||
bench1_top = pulse_generator
|
||||
bench1_chan_width = 300
|
||||
|
||||
# bench1_top = pulse_generator
|
||||
# bench1_chan_width = 300
|
||||
|
||||
# bench2_top = reset_generator
|
||||
# bench2_chan_width = 300
|
||||
bench2_top = reset_generator
|
||||
bench2_chan_width = 300
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
end_flow_with_test=
|
||||
end_flow_with_test=
|
||||
Loading…
Reference in New Issue