From 8c38747d6cbcd147c08c577656e808f73e183b8f Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Thu, 16 Dec 2021 09:53:16 -0700 Subject: [PATCH] revised PR --- .../micro_benchmark/adder/adder_16/adder_16.v | 2 +- .../adder/adder_16/adder_16_clk.v | 39 - .../micro_benchmark/adder/adder_16/wrapper.v | 41 - .../{ => VexRiscv_Symbiflow}/VexRiscv.v | 0 .../vexriscv-verilog_wrap.v | 0 .../processor/{ => vexriscv}/vexriscv_large.v | 0 .../processor/{ => vexriscv}/vexriscv_linux.v | 0 .../processor/{ => vexriscv}/vexriscv_small.v | 0 openfpga_flow/misc/1k_bram.xml | 1177 ----------------- openfpga_flow/misc/1k_bram_openfpga.xml | 352 ----- .../misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys | 102 -- .../misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys | 116 -- ...rac_N4_adder_mem1K_dsp18_40nm_openfpga.xml | 253 ---- ...generate_testbench_example_script.openfpga | 2 +- .../iwls_benchmark_example_script.openfpga | 2 +- ...ite_full_testbench_example_script.openfpga | 2 +- .../micro_benchmark_reg_test.sh | 12 +- openfpga_flow/scripts/run_fpga_flow.py | 2 +- .../k4_series/k4n4_bram/config/task.conf | 4 +- .../signal_gen/config/task.conf | 40 +- 20 files changed, 32 insertions(+), 2114 deletions(-) delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v rename openfpga_flow/benchmarks/processor/vexriscv/{ => VexRiscv_Symbiflow}/VexRiscv.v (100%) rename openfpga_flow/benchmarks/processor/vexriscv/{ => VexRiscv_Symbiflow}/vexriscv-verilog_wrap.v (100%) rename openfpga_flow/benchmarks/processor/{ => vexriscv}/vexriscv_large.v (100%) rename openfpga_flow/benchmarks/processor/{ => vexriscv}/vexriscv_linux.v (100%) rename openfpga_flow/benchmarks/processor/{ => vexriscv}/vexriscv_small.v (100%) delete mode 100644 openfpga_flow/misc/1k_bram.xml delete mode 100644 openfpga_flow/misc/1k_bram_openfpga.xml delete mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys delete mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys delete mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v index 362d8f615..30031ce7d 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v @@ -1,7 +1,7 @@ // Creating a scaleable adder module adder_16(cout, sum, a, b, cin); -parameter size = 3; /* declare a parameter. default required */ +parameter size = 16; /* declare a parameter. default required */ output cout; output [size-1:0] sum; // sum uses the size parameter input cin; diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v deleted file mode 100644 index e42f35414..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v +++ /dev/null @@ -1,39 +0,0 @@ -// Creating a scaleable adder - -module adder_16_clk #( - parameter size = 2 -)( - output reg cout, - output reg [size-1:0] sum, // sum uses the size parameter - input cin, - input [size-1:0] a, b, // 'a' and 'b' use the size parameter - input clk_in, - input rst -); - - -// reg [size-1:0] _sum; -// reg _cout; - -always @(posedge clk_in) begin - if (rst) - {sum,cout} <= 0; - else - {sum,cout} <= a + b + cin; -end - -// assign sum = _sum; -// assign cout = _cout; - -// assign {cout, sum} = a + b + cin; - -endmodule - - - - - - - - - diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v deleted file mode 100644 index 8a54af192..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v +++ /dev/null @@ -1,41 +0,0 @@ -module adder_16_wrapper( - output cout, - output sum_0, - output sum_1, - output sum_2, - output sum_3, - input cin, - input a_0, - input a_1, - input a_2, - input a_3, - input b_0, - input b_1, - input b_2, - input b_3 -); - -wire [4:0] sum; -assign sum_0 = sum[0]; -assign sum_1 = sum[1]; -assign sum_2 = sum[2]; -assign sum_3 = sum[3]; -wire [4:0] a; -assign a_0 = a[0]; -assign a_1 = a[1]; -assign a_2 = a[2]; -assign a_3 = a[3]; -wire [4:0] b; -assign b_0 = b[0]; -assign b_1 = b[1]; -assign b_2 = b[2]; -assign b_3 = b[3]; - -adder_16 DUT( - .cout(cout), - .sum(sum), - .cin(cin), - .a(a), - .b(b) ); - -endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/processor/vexriscv/VexRiscv.v b/openfpga_flow/benchmarks/processor/vexriscv/VexRiscv_Symbiflow/VexRiscv.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv/VexRiscv.v rename to openfpga_flow/benchmarks/processor/vexriscv/VexRiscv_Symbiflow/VexRiscv.v diff --git a/openfpga_flow/benchmarks/processor/vexriscv/vexriscv-verilog_wrap.v b/openfpga_flow/benchmarks/processor/vexriscv/VexRiscv_Symbiflow/vexriscv-verilog_wrap.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv/vexriscv-verilog_wrap.v rename to openfpga_flow/benchmarks/processor/vexriscv/VexRiscv_Symbiflow/vexriscv-verilog_wrap.v diff --git a/openfpga_flow/benchmarks/processor/vexriscv_large.v b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_large.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv_large.v rename to openfpga_flow/benchmarks/processor/vexriscv/vexriscv_large.v diff --git a/openfpga_flow/benchmarks/processor/vexriscv_linux.v b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_linux.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv_linux.v rename to openfpga_flow/benchmarks/processor/vexriscv/vexriscv_linux.v diff --git a/openfpga_flow/benchmarks/processor/vexriscv_small.v b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv_small.v rename to openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v diff --git a/openfpga_flow/misc/1k_bram.xml b/openfpga_flow/misc/1k_bram.xml deleted file mode 100644 index 6b2713350..000000000 --- a/openfpga_flow/misc/1k_bram.xml +++ /dev/null @@ -1,1177 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io_top.outpad io_top.inpad - - - - - - - - - - - - io_right.outpad io_right.inpad - - - - - - - - - - - - io_bottom.outpad io_bottom.inpad - - - - - - - - - - - - io_left.outpad io_left.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk clb.reset - clb.sc_in clb.cin clb.O[7:0] clb.I[8:0] - clb.O[15:8] clb.I[17:9] - clb.sc_out clb.cout - - - - - - - - - - - - - - mult_18.a[0:5] mult_18.b[0:5] mult_18.out[0:11] - mult_18.a[6:11] mult_18.b[6:11] mult_18.out[12:23] - mult_18.a[12:17] mult_18.b[12:17] mult_18.out[24:35] - - - - - - - - - - - - - - - - - - - - - memory.clk - - memory.waddr[2:0] memory.raddr[3:0] memory.data_in[3:0] memory.wen memory.data_out[3:0] - memory.waddr[6:3] memory.raddr[6:4] memory.data_in[7:4] memory.ren memory.data_out[7:4] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - 1 - - - - 1 1 1 - 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ${LUT3_DELAY} - ${LUT3_DELAY} - ${LUT3_DELAY} - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ${LUT4_DELAY} - ${LUT4_DELAY} - ${LUT4_DELAY} - ${LUT4_DELAY} - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/misc/1k_bram_openfpga.xml b/openfpga_flow/misc/1k_bram_openfpga.xml deleted file mode 100644 index 0a9a1d65b..000000000 --- a/openfpga_flow/misc/1k_bram_openfpga.xml +++ /dev/null @@ -1,352 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys deleted file mode 100644 index cd7ff02b5..000000000 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys +++ /dev/null @@ -1,102 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} - -######################### -# Parse input files -######################### -# Read verilog files -${READ_VERILOG_FILE} -# Read technology library -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} - -######################### -# Prepare for synthesis -######################### -# Identify top module from hierarchy -hierarchy -check -top ${TOP_MODULE} -# - Convert process blocks to AST -proc -# Flatten all the gates/primitives -flatten -# Identify tri-state buffers from 'z' signal in AST -# with follow-up optimizations to clean up AST -tribuf -logic -opt_expr -opt_clean -# demote inout ports to input or output port -# with follow-up optimizations to clean up AST -deminout -opt - -opt_expr -opt_clean -check -opt -wreduce -keepdc -peepopt -pmuxtree -opt_clean - -######################## -# Map multipliers -# Inspired from synth_xilinx.cc -######################### -# Avoid merging any registers into DSP, reserve memory port registers first -memory_dff - -######################### -# Run coarse synthesis -######################### -# Run a tech map with default library -techmap -alumacc -share -opt -fsm -# Run a quick follow-up optimization to sweep out unused nets/signals -opt -fast -# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells -memory -nomap -opt_clean - -######################### -# Map logics to BRAMs -######################### -memory_bram -rules ${YOSYS_BRAM_MAP_RULES} -techmap -map ${YOSYS_BRAM_MAP_VERILOG} -opt -fast -mux_undef -undriven -fine -memory_map -opt -undriven -fine - -######################### -# Map pmuxes to muxes -######################### -techmap -map +/pmux2mux.v - -######################### -# Map flip-flops -######################### -techmap -map ${YOSYS_DFF_MAP_VERILOG} -opt_expr -mux_undef -simplemap -opt_expr -opt_merge -opt_rmdff -opt_clean -opt - -######################### -# Map LUTs -######################### -abc -lut ${LUT_SIZE} - -######################### -# Check and show statisitics -######################### -hierarchy -check -stat - -######################### -# Output netlists -######################### -opt_clean -purge -write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys deleted file mode 100644 index 4111e11d8..000000000 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys +++ /dev/null @@ -1,116 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} - -######################### -# Parse input files -######################### -# Read verilog files -${READ_VERILOG_FILE} -# Read technology library -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} - -######################### -# Prepare for synthesis -######################### -# Identify top module from hierarchy -hierarchy -check -top ${TOP_MODULE} -# - Convert process blocks to AST -proc -# Flatten all the gates/primitives -flatten -# Identify tri-state buffers from 'z' signal in AST -# with follow-up optimizations to clean up AST -tribuf -logic -opt_expr -opt_clean -# demote inout ports to input or output port -# with follow-up optimizations to clean up AST -deminout -opt - -opt_expr -opt_clean -check -opt -wreduce -keepdc -peepopt -pmuxtree -opt_clean - -######################## -# Map multipliers -# Inspired from synth_xilinx.cc -######################### -# Avoid merging any registers into DSP, reserve memory port registers first -memory_dff -wreduce t:$mul -techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} -select a:mul2dsp -setattr -unset mul2dsp -opt_expr -fine -wreduce -select -clear -chtype -set $mul t:$__soft_mul# Extract arithmetic functions - -######################### -# Map $alu to carry chain -######################### -alumacc -techmap -map ${YOSYS_ADDER_MAP_VERILOG} - -######################### -# Run coarse synthesis -######################### -# Run a tech map with default library -techmap -alumacc -share -opt -fsm -# Run a quick follow-up optimization to sweep out unused nets/signals -opt -fast -# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells -memory -nomap -opt_clean - -######################### -# Map logics to BRAMs -######################### -memory_bram -rules ${YOSYS_BRAM_MAP_RULES} -techmap -map ${YOSYS_BRAM_MAP_VERILOG} -opt -fast -mux_undef -undriven -fine -memory_map -opt -undriven -fine - -######################### -# Map muxes to pmuxes -######################### -techmap -map +/pmux2mux.v - -######################### -# Map flip-flops -######################### -techmap -map +/adff2dff.v -opt_expr -mux_undef -simplemap -opt_expr -opt_merge -opt_rmdff -opt_clean -opt - -######################### -# Map LUTs -######################### -abc -lut ${LUT_SIZE} - -######################### -# Check and show statisitics -######################### -hierarchy -check -stat - -######################### -# Output netlists -######################### -opt_clean -purge -write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml deleted file mode 100644 index cd12856c5..000000000 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml +++ /dev/null @@ -1,253 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga index e65745efd..0b5cfa232 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --sort_gsb_chan_node_in_edges +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga index dbac0b883..49f1aac73 100644 --- a/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga @@ -2,7 +2,7 @@ # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # This is due to the Fc_in of clock port is set to 0 for global wiring # The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --disp on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga index 347359d53..e3e74a409 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ${OPENFPGA_CLOCK_MODELING} ${OPENFPGA_VPR_DEVICE_LAYOUT} +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 57fae9f46..93cd61c60 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -7,13 +7,13 @@ PYTHON_EXEC=python3.8 # OpenFPGA Shell with VPR8 ############################################## echo -e "Micro benchmark regression tests"; -# run-task benchmark_sweep/counter --debug --show_thread_logs -# run-task benchmark_sweep/mac_units --debug --show_thread_logs +run-task benchmark_sweep/counter --debug --show_thread_logs +run-task benchmark_sweep/mac_units --debug --show_thread_logs -# # Verify MCNC big20 benchmark suite with ModelSim -# # Please make sure you have ModelSim installed in the environment -# # Otherwise, it will fail -# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs +# Verify MCNC big20 benchmark suite with ModelSim +# Please make sure you have ModelSim installed in the environment +# Otherwise, it will fail +run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim run-task benchmark_sweep/signal_gen --debug --show_thread_logs diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index f74514e3c..a333ebb8f 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -698,7 +698,7 @@ def run_rewrite_verilog(): # If there is a template script provided, replace parameters from configuration if not args.ys_rewrite_tmpl: script_cmd = [ - "read_blif -wideports %s" % args.top_module+".blif", + "read_blif %s" % args.top_module+".blif", "write_verilog %s" % args.top_module+"_output_verilog.v" ] command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)] diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf index 91c1237fc..b47eea411 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf @@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=3x2 # Yosys script parameters -yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_sim.v yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams.txt -yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_map.v [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index 0b8fde8fa..6661945a0 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -1,15 +1,22 @@ # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # Configuration file for running experiments + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs + # Each job execute fpga_flow script on combination of architecture & benchmark + # timeout_each_job is timeout for each job + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = false +power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 @@ -17,37 +24,28 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout= -openfpga_clock_modeling=ideal openfpga_fast_configuration= -yosys_adder_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/arith_map.v - [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v -# bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v -# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v -# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v [SYNTHESIS_PARAM] -bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys - -bench0_top = adder_16 +bench0_top = clock_divider bench0_chan_width = 300 -# bench0_top = clock_divider -# bench0_chan_width = 300 +bench1_top = pulse_generator +bench1_chan_width = 300 -# bench1_top = pulse_generator -# bench1_chan_width = 300 - -# bench2_top = reset_generator -# bench2_chan_width = 300 +bench2_top = reset_generator +bench2_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= +end_flow_with_test= \ No newline at end of file