$_soc is set per platform, no point in duplicating _CHIPNAME to
explicitly set the information provided by $_CHIPNAME itself.
So move it out after the check for CHIP_NAME
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I60d30d6a9a2ce352f66c5bc03075e4ba638e3062
Reviewed-on: https://review.openocd.org/c/openocd/+/7889
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
STM32WBA5x have a single bank flash up to 1MB
Change-Id: I3d720e202f0fdd89ecd8aa7224653ca5a7ae187b
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7694
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Added NPCX flash driver to support the Nuvoton NPCX4/K3 series
microcontrollers. Add config file for these series.
Change-Id: I0b6e128fa51146b561f422e23a98260594b1f138
Signed-off-by: Luca Hung <YCHUNG0@nuvoton.com>
Signed-off-by: Mulin CHao <mlchao@nuvoton.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7794
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add support for the TI K3 family AM62A7 SoC.
For further details, see https://www.ti.com/lit/pdf/spruj16a
Change-Id: Ie69bde4895f34b04f9967f63d1ca9c8149c50b8a
Signed-off-by: Jason Kacines <j-kacines@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7854
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Add links for the SoCs are supported by the conf file for future
reference.
Change-Id: Ic5b7786ef3ac31414fe2ce56c1237a18ce99aaa1
Signed-off-by: Jason Kacines <j-kacines@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7853
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Sufficient to probe both cores via multiple APs.
No support listed for jtag in the datasheet or usermanual.
Tested against a BW-16 board:
https://www.amebaiot.com/en/amebad/#partner_bw16
Change-Id: Idf82085e7b7327fdf3d6d668e6fb59eff6e0431b
Signed-off-by: Karl Palsson <karlp@tweak.au>
Reviewed-on: https://review.openocd.org/c/openocd/+/7847
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
This commit provides startup files for the Synopsys DesignWare ARC
HSDK-4xD board. These have been adapted from the corresponding
snps_hsdk.cfg files, the only functional change being the JTAG IDs for
the new board's CPU cores.
Change-Id: I19a0cd13bc09de90cfe2a7cccf1239e459fd8077
Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7829
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
ESP32-C6 and ESP32-H2 are single core riscv targets.
Change-Id: If92429de4fb67a040f303a54177d61b70e1ea281
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.
Change-Id: I825dd4fddb88e5514429d49ab13869ee6b9a28fc
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ie3413d3149388b17bc0199409ce86d3eb7cf5ee2
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ifb0122f3b98a767f27746409499733b70fb7d0e8
Reviewed-on: https://review.openocd.org/c/openocd/+/7747
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I36c86fe4ebc99928ce48a5bff8cb9580a0fa3ac0
Reviewed-on: https://review.openocd.org/c/openocd/+/7746
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9181737d83eeba4e983b6a455b8a1523f2576dd2
Reviewed-on: https://review.openocd.org/c/openocd/+/7745
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Consolidate commonly used commands and variables from
chip config files into functions in esp_common.cfg.
This includes "jtag newtap," "target create,"and "configure -event."
Enhances code reusability and simplifies maintenance.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9e8bf07a4a15d4544ceb564607dea66837381d70
Reviewed-on: https://review.openocd.org/c/openocd/+/7744
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ifb0122f3b98a767f27746409499733b70fb7d0e8
Reviewed-on: https://review.openocd.org/c/openocd/+/7747
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I36c86fe4ebc99928ce48a5bff8cb9580a0fa3ac0
Reviewed-on: https://review.openocd.org/c/openocd/+/7746
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9181737d83eeba4e983b6a455b8a1523f2576dd2
Reviewed-on: https://review.openocd.org/c/openocd/+/7745
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Consolidate commonly used commands and variables from
chip config files into functions in esp_common.cfg.
This includes "jtag newtap," "target create,"and "configure -event."
Enhances code reusability and simplifies maintenance.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9e8bf07a4a15d4544ceb564607dea66837381d70
Reviewed-on: https://review.openocd.org/c/openocd/+/7744
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Use configurable virtex pld driver to add support for more
xilinx fpga families.
Change-Id: Iff10c8c511787734fa289bdba15f03131d51e071
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7352
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The current cJTAG to JTAG switching commands for TI chips are not
particularly reliable, especially on chips with accurate timing.
On a Raspberry Pi the existing sequence has (depending on cabling and
chip) a ~50% chance of working, on a much better-behaved FT2232H
it doesn't manage to enable full JTAG at all.
This change runs a bunch of test-idle cycles before actually attempting
to switch to full JTAG. This makes the switch reliable even at high
clock speeds (>100kHz) and from precise sources like the FT2232H.
Change-Id: I9293e884bf3e9606d529756ae4483b844d3c39db
Reported-by: Phil Wiggum <p1mail2015@mail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/375/
Signed-off-by: Lorenz Brun <lorenz@brun.one>
Reviewed-on: https://review.openocd.org/c/openocd/+/7419
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This patch adds support for the NXP QN908x family of Bluetooth
microcontrollers, such as the QN9080. This chip features a Cortex-M4F
with 512 KiB of flash on all the available versions, although the
documentation suggests that there might be 256 kB versions as well.
The initial support allows to read, erase and write the whole user flash
area. Three new sub-commands under the new "qn908x" command are added
in this patch as well: disable_wdog to disabled the watchdog,
mass_erase to perform a mass erase and allow_brick to allow programming
images that disable the SWD interface.
Disabling the watchdog is required after a "reset halt" in order to run
the CRC algorithm from RAM when verifying the chip. However, this is not
done automatically on probing or other initialization since disabling
the watchdog might interfere with debugging real applications.
The "mass_erase" command allows to erase the whole flash without
probing it, since in some scenarios the chip can be locked such that no
flash or ram can be accessed from the SWD interface, allowing only to
run a mass_erase to be able to flash the program.
The flashing process allows to compute a checksum, similar to the
lpc2000 driver "calc_checksum" but done over a different region of the
memory. This checksum is required to be present for the QN908x
bootloader ROM to boot, and otherwise is useless. As with the lpc2000
design, verification when using "calc_checksum" is expected to fail if
the checksum was not valid in the image being verified.
This was manually tested on a QN9080, including the scan-view,
AddressSanitizer/UBSan and test coverage configurations.
Change-Id: Ibd6d8f3608654294795085fcaaffb448b77cc58b
Co-developed-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
Signed-off-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
Signed-off-by: iosabi <iosabi@protonmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5584
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This change adds the extensa sample target and board configurations.
it removes the obsoleted vd_xtensa_jtag.cfg from targets.
Change-Id: I9d4d25abde46c0b15e5211a973012447872cb405
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7723
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
this new STM32 series family introduces 2 devices:
STM32C011xx (0x443) and STM32C031xx (0x453)
both devices have 32 Kbytes single flash bank.
Change-Id: I4e890789e44e3b174c0e9c0e1068383ecdbb865f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6874
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Added support for TMS570LC43xx series parts. This uses the pre-existing
ti_tms570.cfg parent config. In ti_tms570.cfg, dbgbase was changed.
Note 1: Based on the following TI E2E post, the previous dbgbase was wrong
and the new value isn't due to a difference in parts.
Link: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1106954/tms570ls3137-debugging-with-openocd
Note 2: Both the previous dbgbase and the one suggested in the TI E2E post
have the 2 LSB set. In the current version of OpenOCD, this will cause
cortex_a_read_cpu_memory_fast and cortex_a_write_cpu_memory_fast to fail
due to an alignment checks in
mem_ap_<read/write>_buf_noincr()->mem_ap_<read/write>().
In all other uses of dbgbase for arm cortex parts, the 2 LSB are masked
and ignored.
Change-Id: Ic936722e5a4cfc7161b0df1fe3325ee12fd901c6
Signed-off-by: Phil Kirkpatrick <p.kirkpatrick@reflexaerospace.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7682
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add missing ID codes and ignore the version in the ID.
Change-Id: Idd2d3a5eddb6995f3af1c45afd2adf76ce3442bf
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7386
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Integrate a rescue mode inspired by [1].
The current OpenOCD must be restarted before normal work with the RP2040
because the rescue debug port must not be activated (or the target
is reset every 'dap init'). To continue without restarting OpenOCD
we would need to switch off the configured rescue dap.
Change-Id: Ia05b960f06747063550c166e461939d92e232830
Link: [1] https://github.com/raspberrypi/openocd/blob/rp2040/tcl/target/rp2040-rescue.cfg
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7327
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Same mechanism as in stm32f1x.cfg reused here.
Change-Id: I81f02feb2b655e8259341b22180f3a8b82e28d05
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7438
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The rtos hwthread has been merged in 2019 with commit 85ba2dc4c6
("rtos/hwthread: add hardware-thread pseudo rtos").
During review in patchset 19 the name of the rtos has been changed
from 'hawt' to 'hwthread'.
Some target config file was already merged ready for hwthread, but
keeping the relevant lines commented and still reporting the old
name.
Enable rtos hwtread to the target that were supposed to use it.
Fix the name of the rtos.
Change-Id: I877862dcdba39f26462bb542bac06d1a5f5f222d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7384
Tested-by: jenkins
This patch is picked from the tcl part of OpenOCD-Nuvoton's commit
("flash: supported Nuvoton M4 series. jtag: Used HW reset instead of
auto reset. tcl: added a configuration file for Nuvoton M4 series.") [1]
to support the communication with Nuvoton's Cortex-M4 chips: M541 &
NUC442/472 series.
This patch has been tested with Nuvoton's NuTiny-SDK-NUC472 development
board [2].
The code comes from the commit basically. Jian-Hong Pan tweaked for the
compatibility with current OpenOCD. So, leave the author as Zale Yu.
[1]: https://github.com/OpenNuvoton/OpenOCD-Nuvoton/commit/c2d5b8bfc705
[2]: https://www.nuvoton.com/export/resource-files/UM_NuTiny-SDK-
NUC472_EN_Rev1.02.pdf
Signed-off-by: Zale Yu <cyyu@nuvoton.com>
Signed-off-by: Jian-Hong Pan <chienhung.pan@gmail.com>
Change-Id: I27ac58dd1c98a76e791a4f1117c31060cf5522e8
Reviewed-on: https://review.openocd.org/c/openocd/+/7330
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
rp2040-core0.cfg configuration file was intended for a special adapter
which selects a SWD multidrop target on its own. This means
that rp2040-core0.cfg is totally unusable with a standard SWD
adapter. The file was marked as deprecated in 0.12 release.
The reworked rp2040.cfg can be restricted to use just one core:
openocd ... -c 'set USE_CORE 0' -f target/rp2040.cfg
Remove the obsoleted config.
Change-Id: Id886471622bb4a8cb83f5c4c3660657407aaaf74
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7326
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add the variable selected configuration for SMP debug with rtos hwthread.
Use SMP by default.
Change-Id: I1c37d91688a3ab58d65c15686737892965711adc
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7242
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The target nds32 and its companion adapter aice have not received
any real improvement since 2013.
It has been hard to keep them aligned during the evolution of
OpenOCD code, with no way for maintainers to really check if they
are still working.
No real documentation is present for them in OpenOCD.
The nds32 code triggers ~50 errors/warnings with scan-build.
The arch nds32 has been dropped from Linux kernel v5.18-rc1.
For all the reasons above, this code has been deprecated with
commit 2e5df83de7 ("nds32: deprecate it, together with aice
adapter driver") and tagged to be dropped before v0.13.0.
Let it r.i.p. in OpenOCD git history.
While there, drop from checkpatch list the camelcase symbols that
where only used in this code.
Change-Id: Ide52a217f2228e9da2f1cc5036c48f3536f26952
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7382
Tested-by: jenkins
The existing rp2040-core0.cfg configuration file was intended
for a special adapter which selects a SWD multidrop target on its own.
This means that rp2040-core0.cfg is totally unusable with a standard SWD
adapter.
To fix the problem, mark rp2040-core0.cfg as deprecated and
add rp2040.cfg, a basic config file with multidrop target selection.
Change-Id: I5194e42f529a2d9645481424b7c66ab61efa44ee
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7275
Tested-by: jenkins
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
instrument "target/stm32x5x_common.cfg" used by both STM32L5x/U5x
to support HLA adapters like "interface/stlink.cfg" in non-secure mode
if the device switches to secure mode, the debug session will be
stopped immediately (with an explanatory message).
Change-Id: I645fdd55e3448ef82d0ddcc396f42fd7b2f39ac3
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reported-by: Patrik Bachan <diggit@users.sourceforge.net>
Fixes: https://sourceforge.net/p/openocd/tickets/317/
Reviewed-on: https://review.openocd.org/c/openocd/+/6546
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Some config changes required to run ESP32-S3 with full feature set
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I38022bb5ff5830e1cf9d11d6fe795ea99d91e9db
Reviewed-on: https://review.openocd.org/c/openocd/+/7254
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Some config changes required to run ESP32-S2 with full feature set
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ie0a742442254ec6e95d4e05be40213b079a94dab
Reviewed-on: https://review.openocd.org/c/openocd/+/7253
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Some config changes required to run ESP32 with full feature set
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I484324f8497ec7934bb73164c638fc5f6460fcc4
Reviewed-on: https://review.openocd.org/c/openocd/+/7252
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The work area should be backed up.
The flash probe runs an algorithm on the target CPU.
The flash is probed during gdb connect if gdb_memory_map is enabled
(is enabled by default).
Without backup the target memory gets corrupted on gdb connect.
Change-Id: I3344b9dc6cbf904d49f3b05ab104b541d1d63422
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7257
Tested-by: jenkins
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Since all the device definition when accessing device from jtag is also
valid when accessing from swd, lets make sure the configuration can
handle the same.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I5af071137fd8c3b52cc4ef72401f8eba952f9cad
Reviewed-on: https://review.openocd.org/c/openocd/+/7090
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The STM32L5 and U5 devices have DBGMCU_CR trace related bits changed
wrt other STM32 devices.
Fix the setting in configuration script.
Change-Id: I0bbc48e7b1290b603c6966cf5ddd42df389e6ede
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7117
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
- Config files for DAP/JTAG and DAP/SWD systems
- Xtensa core config definitions for NXP RT685 with Xtensa HiFi DSP
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I9c3280052073d86e09c7553de661eb8662a95c4a
Reviewed-on: https://review.openocd.org/c/openocd/+/7145
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
While reviewing on gerrit the change
https://review.openocd.org/6932/
it get clear that the missing documentation on stm32f4x's code
was triggering errors in the new change.
OpenOCD is currently unable to read traces, but these can be
hopefully be read with some other tool.
Document the settings for enabling trace on stm32[fl]4x.
Change-Id: Ibae77a53de16375d3d500e728678740095547009
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6945
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
With commit dc7b32ea4a ("armv7m_trace: get rid of the old tpiu
code") the target's event "trace-config" has been deprecated.
Create the TPIU device.
Replace the target's event "trace-config" with tpiu's event
"pre-enable" in the STM32 devices that require enabling the trace
clock _before_ programming the TPIU.
Make the script multi-instance-able in case it's used for JTAG
chained devices.
Uniform the code in STM32F4x with the other scripts.
Remove the empty event from STM32WLx.
Change-Id: Ifda219c3c5f37e03072a88168611cf505eb630b7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6681
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Generic Xtensa LX support extends the original Espressif/Xtensa
patch-set to support arbitrary Xtensa configurations, as defined in
a core-specific .cfg file. Not yet fully-featured. Additional
functionality to be added:
- Xtensa NX support
- DAP/SWD support
- File-IO support
- Generic Xtensa multi-core support
Valgrind-clean, no new Clang analyzer warnings
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I08e7bf8fa57c25b5d0cb75a1aa7a2ac13a380c52
Reviewed-on: https://review.openocd.org/c/openocd/+/7055
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This patch adds support for DAP interface to Cadence vdebug driver.
It implements a new transport layer for dapdirect_swd.
Change-Id: I64b02a9e1ce91e552e07fca692879655496f88b6
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6965
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/ target| while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: I7b2610300b24cccd07bfa6fb5f1266970d5d3a1b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7027
Tested-by: jenkins
The SPDX tag is aimed at machine handling and it's thus expected
to be placed in the first line.
Change-Id: I3992856eeb28b333c38d010ef286e22471ede263
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7026
Tested-by: jenkins
OpenOCD project is switching to SPDX tags.
Replace the few FSF boilerplate in tcl folder.
Change-Id: I15b146eb77cc491ed7355178f684f3e76fc763b4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7025
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
In order to facilitate debugging multiple cores, specify the coreid and
the hwthread rtos in the imx8m target configuration.
Change-Id: Ibd871517a160ceca15002fb10e27cb793f14d086
Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Reviewed-on: https://review.openocd.org/c/openocd/+/7019
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
ESP32-S3 is a dual core Xtensa SoC
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I44e17088030c96a9be9809f6579a4f16dbfc5794
Reviewed-on: https://review.openocd.org/c/openocd/+/6990
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
ESP32 is a dual core Xtensa SoC
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I76fb184aa38ab9f4e30290c038b5ff8850060750
Reviewed-on: https://review.openocd.org/c/openocd/+/6989
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add Ampere Altra ("Quicksilver") and Ampere Altra Max ("Mystique")
target/board configuration files.
The target configuration file supports silicon and emulation.
The board configuration files support 1 and 2 socket platforms.
Tested on Ampere emulation and silicon
Change-Id: I036c798a50624e30ab51ccd2895b6f60c40be096
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5591
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
ESP32-S2 is a single core Xtensa chip.
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I2fb32978e801af5aa21616c581691406ad7cd6bb
Reviewed-on: https://review.openocd.org/c/openocd/+/6940
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The LS1028A is similar to the LS1088A, except that it has 2 CPUs (and
different ethernet capabilities). From a JTAG perspective, all that's
different is the number of CPUs and the TAPID.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: Iba3a0ecfbf82cfcfeb7eea42d52121c3b9dc93a2
Reviewed-on: https://review.openocd.org/c/openocd/+/6976
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Several Layerscape processors (LS1088A, LS2088A, LS2160A, and LS1028A)
share a common architecture. Break out the common setup from the LS1088
config in preparation for adding the LS1028A. There's no official name
for this series of processors, but NXP refers to them as "chassis
generation 3" in U-Boot, so we'll go with that too.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: Ic6f89f95c678101f54579bcaa5d79c5b67ddf50a
Reviewed-on: https://review.openocd.org/c/openocd/+/6975
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Added support for the new Renesas RISC-V
device: RZ/Five
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Change-Id: Id8ba29b83528c0bfe4f9b4ed21b0151a6e853bd7
Reviewed-on: https://review.openocd.org/c/openocd/+/6974
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Added support for two new devices: RZ/G2LC and RZ/G2UL
Change-Id: Iec6ba88c1d279f50808b060343b45c796bbfdbfc
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6972
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Added bluenrg-lps support
Added file for the board steval-idb012v1
Fixed size_info information using a mask
Changed the if condition in bluenrg-x.cfg to be valid only for bluenrg-1 and bluenrg-2
Signed-off-by: Salvatore Giorgio PECORINO <salvatore-giorgio.pecorino@st.com>
Change-Id: Ic0777ec0811ee6fac7d5e1d065c4629e47d84a1f
Reviewed-on: https://review.openocd.org/c/openocd/+/6928
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Conflicts:
tcl/target/gd32vf103.cfg
I kept our version, except I changed the flash device as happened in
mainline. Once this file settles down in mainline, we can copy it
wholesale into this fork.
Change-Id: I4c5b21fec0734b5e08eba392883e006a46386b1c
The flash is compatible with stm32f1x, reuse the driver.
Extend the size of work area to RAM size of the smallest device.
Stop watchdogs before flash programming.
Change-Id: I67a7654a6e196f9d4b2409edaa7990c53334437e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6711
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Replace deprecated commands 'mem2array' and 'array2mem' with
new Tcl commands 'read_memory' and 'write_memory'.
Change-Id: I116d995995396133ca782b14cce02bd1ab917a4e
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6859
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The LS1046A is a quad-core processor from NXP in the layerscape family.
This SoC is a bit tricky to program: while the AArch64 CPUs are
little-endian, most of the peripherals are big-endian. Care must be
taken when interpreting memory reads/writes. This processor is in the
same family as the ls1012a, so the setup is similar.
If you use OpenOCD to attach early in the boot process, only the cpu0
may be available. Trying to halt other CPUs will fail. To avoid this,
defer examination of cpus 1-3, and provide a core_up helper (like e.g.
zynqmp).
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: If5a1a9441fb35fea3e05dc708b42e0cb3bbf2a54
Reviewed-on: https://review.openocd.org/c/openocd/+/6854
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Original TLC syntax uses 'set varname' to retrieve the value of
variable 'varname'. Such archaic syntax is still valid, but the
shorter '$varname' makes the code easier to read.
Replace 'set varname' with '$varname'.
While there, remove some useless curly brackets.
Change-Id: I27310e8c05afe56ea8bd0e41d4ae2c34447b725c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6863
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add support for the latest in TI k3 family AM625 SoC.
For further details, see https://www.ti.com/lit/pdf/spruiv7
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ia54d0eab1c30a973afb1c2c61f4c5a72d29d9b78
Reviewed-on: https://review.openocd.org/c/openocd/+/6798
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add support for the latest in TI k3 family J721S2 SoC.
For further details, see http://www.ti.com/lit/pdf/spruj28
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I608ab4513ffb6b5c4166ba423e7d0dddbbb3bbfd
Reviewed-on: https://review.openocd.org/c/openocd/+/6796
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Since we can detect the type of target as well, reuse the _cpu_no_smp_up
function name and use the target name to simplify the _up function and
maintain consistency with what we introduced for r5.
Lets introduce gdb-attach event in a much cleaner fashion.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
While at it, fix a minor type of s/are/as in "Set Default target are
core 0" and simplify the foreach usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I3259b7c3ae4c71b06d921edfaefe17c03bb673dc
Reviewed-on: https://review.openocd.org/c/openocd/+/6616
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Since we can detect the type of target as well, make the attach
function name generic for the follow on cleanup patch on armv8 to use
as well.
Lets introduce gdb-attach event in a much cleaner fashion. We can
introduce a simpler r5_up function since we now have more descriptive
core names making the individual descriptive procs redundant.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I31506bb2b86e63638082640eb72aa7c4c9575e93
Reviewed-on: https://review.openocd.org/c/openocd/+/6617
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
R5 targets are currently named r5.0..n and the only way for user to
determine the actual type is external documentation. Lets just rename
the target names to make them descriptive to not require external
documentation for finding which R5 to connect to.
NOTE: we leave the _mcu_r5_cores _main0_r5_cores _main1_r5_cores alone
for now to allow existing startup proc functions to work, but we will
drop it in the follow on patch.
Previously:
Info : starting gdb server for j721e.cpu.r5.0 on 3336
Info : Listening on port 3336 for gdb connections
Info : starting gdb server for j721e.cpu.r5.1 on 3337
Info : Listening on port 3337 for gdb connections
Info : starting gdb server for j721e.cpu.r5.2 on 3338
Info : Listening on port 3338 for gdb connections
Info : starting gdb server for j721e.cpu.r5.3 on 3339
Info : Listening on port 3339 for gdb connections
Info : starting gdb server for j721e.cpu.r5.4 on 3340
Info : Listening on port 3340 for gdb connections
Info : starting gdb server for j721e.cpu.r5.5 on 3341
Info : Listening on port 3341 for gdb connections
With this patch:
Info : starting gdb server for j721e.cpu.mcu_r5.0 on 3336
Info : Listening on port 3336 for gdb connections
Info : starting gdb server for j721e.cpu.mcu_r5.1 on 3337
Info : Listening on port 3337 for gdb connections
Info : starting gdb server for j721e.cpu.main0_r5.0 on 3338
Info : Listening on port 3338 for gdb connections
Info : starting gdb server for j721e.cpu.main0_r5.1 on 3339
Info : Listening on port 3339 for gdb connections
Info : starting gdb server for j721e.cpu.main1_r5.0 on 3340
Info : Listening on port 3340 for gdb connections
Info : starting gdb server for j721e.cpu.main1_r5.1 on 3341
Info : Listening on port 3341 for gdb connections
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I2989efe3ae3e16754f98fa1dc9363ec4c898f7c3
Reviewed-on: https://review.openocd.org/c/openocd/+/6627
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The MCU is present on few of the SoCs and is meant as General Purpose
(GP) MCU of the system. Lets rename it to make clear what we are
debugging - esp when multiple MCUs are present in the system.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I16132d321daf6e9b1d893fe6f92026d5aa9eb152
Reviewed-on: https://review.openocd.org/c/openocd/+/6619
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The M3 is the system controller of the system. Lets rename it to make
clear what we are debugging - esp when multiple MCUs are present in the
system.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I4cd03b6068b8ce140fd254f9dd88151c4c7006d7
Reviewed-on: https://review.openocd.org/c/openocd/+/6618
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add gdb-attach event to call the "up" function of m3 and m4 allowing for
more seamless integration with gdb for end users. We still retain _up
functions for non-gdb functionality.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I2e51fdbd8756f156551e589c748c3a338afa655c
Reviewed-on: https://review.openocd.org/c/openocd/+/6615
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Nishanth Menon
Tarek BOCHKATI
Tim Newsome
Luca Hung
Kaelin Laundry
Jason Kacines
Karl Palsson
Artemiy Volkov
Erhan Kurubas
Daniel Anselmi
Lorenz Brun
iosabi
Jacek Wuwer
Dominik Wernberger
Tarek BOCHKATI
Phil Kirkpatrick
Julien Massot
Tomas Vanek
Andreas Fritiofson
Antonio Borneo
Zale Yu
Kyle Schwarz
Rocco Marco Guglielmi
Ian Thompson
Toms Stūrmanis
Adrien Grassein
Alvin Šipraga
Daniel Goehring
Erhan Kurubas
Sean Anderson
micbis
Salvatore Giorgio PECORINO
Markus Reiter
Marc Schink