flash/stm32l4x: support STM32WBA5xx devices
STM32WBA5x have a single bank flash up to 1MB Change-Id: I3d720e202f0fdd89ecd8aa7224653ca5a7ae187b Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com> Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7694 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tarek BOCHKATI
Tomas Vanek
parent
fb52ba4fa1
commit
870769b0ba
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@ -57,6 +57,9 @@
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*/
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/* STM32WBxxx series for reference.
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*
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* RM0493 (STM32WBA52x)
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* http://www.st.com/resource/en/reference_manual/dm00821869.pdf
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*
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* RM0434 (STM32WB55/WB35x)
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* http://www.st.com/resource/en/reference_manual/dm00318631.pdf
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@ -346,6 +349,10 @@ static const struct stm32l4_rev stm32u57_u58xx_revs[] = {
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{ 0x2001, "X" }, { 0x3000, "C" },
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};
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static const struct stm32l4_rev stm32wba5x_revs[] = {
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{ 0x1000, "A" },
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};
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static const struct stm32l4_rev stm32wb1xx_revs[] = {
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{ 0x1000, "A" }, { 0x2000, "B" },
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};
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@ -579,6 +586,18 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
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.otp_base = 0x0BFA0000,
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.otp_size = 512,
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},
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{
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.id = DEVID_STM32WBA5X,
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.revs = stm32wba5x_revs,
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.num_revs = ARRAY_SIZE(stm32wba5x_revs),
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.device_str = "STM32WBA5x",
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.max_flash_size_kb = 1024,
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.flags = F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
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.flash_regs_base = 0x40022000,
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.fsize_addr = 0x0FF907A0,
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.otp_base = 0x0FF90000,
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.otp_size = 512,
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},
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{
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.id = DEVID_STM32WB1XX,
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.revs = stm32wb1xx_revs,
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@ -1993,6 +2012,12 @@ static int stm32l4_probe(struct flash_bank *bank)
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stm32l4_info->bank1_sectors = num_pages / 2;
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}
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break;
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case DEVID_STM32WBA5X:
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/* single bank flash */
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page_size_kb = 8;
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num_pages = flash_size_kb / page_size_kb;
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stm32l4_info->bank1_sectors = num_pages;
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break;
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case DEVID_STM32WB5XX:
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case DEVID_STM32WB3XX:
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/* single bank flash */
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@ -103,6 +103,7 @@
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#define DEVID_STM32L55_L56XX 0x472
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#define DEVID_STM32G49_G4AXX 0x479
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#define DEVID_STM32U57_U58XX 0x482
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#define DEVID_STM32WBA5X 0x492
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#define DEVID_STM32WB1XX 0x494
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#define DEVID_STM32WB5XX 0x495
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#define DEVID_STM32WB3XX 0x496
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@ -0,0 +1,106 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32wbax family
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#
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# stm32wba devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32wbax
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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set _CPUTAPID 0x6ba00477
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} else {
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# SWD IDCODE (single drop, arm)
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set _CPUTAPID 0x6ba02477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x0FF90000 0 0 0 $_TARGETNAME
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# Common knowledges tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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# the safe side.
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#
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# Note that there is a pretty wide band where things are
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# more or less stable, see http://openocd.zylin.com/#/c/3366/
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adapter speed 500
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event reset-init {
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# CPU comes out of reset with HSION | HSIRDY.
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# Use HSI 16 MHz clock, compliant even with VOS == 2.
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# 1 WS compliant with VOS == 2 and 16 MHz.
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mmw 0x40022000 0x00000001 0x0000000E ;# FLASH_ACR: Latency = 1
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mmw 0x56020C00 0x00000100 0x00000000 ;# RCC_CR |= HSION
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mmw 0x56020C1C 0x00000000 0x00000002 ;# RCC_CFGR1: SW=HSI16
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# Boost JTAG frequency
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adapter speed 4000
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}
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$_TARGETNAME configure -event reset-start {
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# Reset clock is HSI (16 MHz)
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adapter speed 2000
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}
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$_TARGETNAME configure -event examine-end {
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
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mmw 0xE0042004 0x00000006 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0042008 0x00001800 0
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}
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
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lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
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proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
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targets $_targetname
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}
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$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
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