flash/stm32l4x: support STM32C0x devices
this new STM32 series family introduces 2 devices: STM32C011xx (0x443) and STM32C031xx (0x453) both devices have 32 Kbytes single flash bank. Change-Id: I4e890789e44e3b174c0e9c0e1068383ecdbb865f Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6874 Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp> Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Tarek BOCHKATI
Tomas Vanek
parent
5c46a5de49
commit
4defa3b1e3
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@ -80,6 +80,12 @@
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* http://www.st.com/resource/en/reference_manual/dm00451556.pdf
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*/
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/* STM32C0xxx series for reference.
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*
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* RM0490 (STM32C0x1)
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* http://www.st.com/resource/en/reference_manual/dm00781702.pdf
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*/
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/* STM32G0xxx series for reference.
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*
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* RM0444 (STM32G0x1)
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@ -263,7 +269,7 @@ struct stm32l4_wrp {
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};
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/* human readable list of families this drivers supports (sorted alphabetically) */
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static const char *device_families = "STM32G0/G4/L4/L4+/L5/U5/WB/WL";
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static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U5/WB/WL";
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static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
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{ 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
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@ -273,6 +279,15 @@ static const struct stm32l4_rev stm32l43_l44xx_revs[] = {
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{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
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};
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static const struct stm32l4_rev stm32c01xx_revs[] = {
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{ 0x1000, "A" }, { 0x1001, "Z" },
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};
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static const struct stm32l4_rev stm32c03xx_revs[] = {
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{ 0x1000, "A" }, { 0x1001, "Z" },
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};
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static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
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{ 0x1000, "A" },
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};
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@ -371,6 +386,30 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
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.otp_base = 0x1FFF7000,
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.otp_size = 1024,
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},
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{
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.id = DEVID_STM32C01XX,
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.revs = stm32c01xx_revs,
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.num_revs = ARRAY_SIZE(stm32c01xx_revs),
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.device_str = "STM32C01xx",
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.max_flash_size_kb = 32,
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.flags = F_NONE,
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.flash_regs_base = 0x40022000,
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.fsize_addr = 0x1FFF75A0,
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.otp_base = 0x1FFF7000,
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.otp_size = 1024,
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},
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{
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.id = DEVID_STM32C03XX,
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.revs = stm32c03xx_revs,
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.num_revs = ARRAY_SIZE(stm32c03xx_revs),
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.device_str = "STM32C03xx",
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.max_flash_size_kb = 32,
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.flags = F_NONE,
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.flash_regs_base = 0x40022000,
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.fsize_addr = 0x1FFF75A0,
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.otp_base = 0x1FFF7000,
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.otp_size = 1024,
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},
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{
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.id = DEVID_STM32G05_G06XX,
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.revs = stm32g05_g06xx_revs,
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@ -1855,6 +1894,8 @@ static int stm32l4_probe(struct flash_bank *bank)
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}
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break;
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case DEVID_STM32L43_L44XX:
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case DEVID_STM32C01XX:
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case DEVID_STM32C03XX:
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case DEVID_STM32G05_G06XX:
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case DEVID_STM32G07_G08XX:
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case DEVID_STM32L45_L46XX:
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@ -87,6 +87,8 @@
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/* Supported device IDs */
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#define DEVID_STM32L47_L48XX 0x415
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#define DEVID_STM32L43_L44XX 0x435
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#define DEVID_STM32C01XX 0x443
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#define DEVID_STM32C03XX 0x453
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#define DEVID_STM32G05_G06XX 0x456
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#define DEVID_STM32G07_G08XX 0x460
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#define DEVID_STM32L49_L4AXX 0x461
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@ -0,0 +1,74 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32c0x family
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#
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# stm32c0 devices support SWD transports only.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32c0x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 6kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x1800
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# SWD IDCODE (single drop, arm)
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set _CPUTAPID 0x0bc11477
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
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# reasonable default
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adapter speed 2000
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event examine-end {
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# Enable DBGMCU clock
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# RCC_APB1ENR |= DBGMCUEN
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mmw 0x4002103C 0x08000000 0
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
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mmw 0x40015804 0x00000006 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ |= DBG_WDGLS_STOP | DBG_WWDG_STOP
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mmw 0x40015808 0x00001800 0
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}
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