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Author SHA1 Message Date
cgsfv 10a2823191 Read memory words individually if burst read fails 2018-09-17 13:53:35 -07:00
Ryan Macdonald 631f6cd55b More style fixes 
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
 2018-08-31 14:30:17 -07:00
Ryan Macdonald 3516fd5019 Style fixes 
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
 2018-08-31 14:29:09 -07:00
Ryan Macdonald 583c90e87c Add pass message for SBA and compliance tests 
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
 2018-08-31 14:26:32 -07:00
Megan Wachs 4b29af433d Merge remote-tracking branch 'origin/riscv' into sba_tests 2018-08-31 09:02:55 -07:00
Megan Wachs 24513fe51f riscv-compliance: fix comment typo 2018-08-30 15:37:15 -07:00
Megan Wachs 7448f8780a riscv-compliance: fix whitespace 2018-08-30 11:30:14 -07:00
Megan Wachs 934440b80e riscv-compliance: incorporate review feedback 2018-08-30 11:26:05 -07:00
Tim Newsome 164415cfbe
Merge branch 'riscv' into sba_tests 2018-08-29 15:55:30 -07:00
Megan Wachs 34ee883aef Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebase 2018-08-29 15:47:54 -07:00
Tim Newsome b4b2ec7d2d
Add command to expose custom registers (#293) 
* Added `riscv expose_custom` command.

Seems to work for reading. I need to do some more testing for writes, as
well as minor cleanup.

Change-Id: I85d5d00897d5da4add4a6643b538be37d31a016f

* Conform to OpenOCD style.

Change-Id: I40a316f06f418d2b63d9e11aea03ef51da8d8faf

* Free all the memory allocated by register init.

Change-Id: I04e35ab54613f99708cee85e41fef989079adefc

* Properly document `riscv expose_custom`.

Change-Id: Id78a02b7a00c161df80f11b521a306e0cf3d7478
 2018-08-29 14:22:50 -07:00
Tim Newsome 684d7d6764
Remove unused variable. (#284) 
Change-Id: Iedebce86b5d914ff612a4747ffdc6f776edca783
 2018-08-20 12:42:30 -07:00
Tim Newsome a51ab8ddf6 Add RISC-V support. 
This supports both 0.11 and 0.13 versions of the debug spec.

Support for `-rtos riscv` will come in a separate commit since it was
easy to separate out, and is likely to be more controversial.

Flash support for the SiFive boards will also come in a later commit.

Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4578
Tested-by: jenkins
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
 2018-07-24 13:07:26 +01:00
Tim Newsome ead2a595b8 Use work area instead of riscv-specific config 
Per review requested at http://openocd.zylin.com/#/c/4578/3

Change-Id: I1a8117665d38844dc1479f33b4f9b7c8f9f101c8
 2018-07-16 14:43:15 -07:00
Tim Newsome 2a6332f620 Update debug defines to match spec 
The main difference is we need to deal with hartsello/hartselhi. (Note
that there's a compile-time limit to 16 harts, but that can be changed.)
My largest target has 4 harts, so I can't tell how well this really
works. But it doesn't break anything.

Fixes #240.

Change-Id: Ie1a2a789b5e00f55174994568749da1cf3a33b92
 2018-06-06 13:43:35 -07:00
Tim Newsome ab7ab8a867
Merge pull request #261 from riscv/trigger_enum 
Delay trigger enumeration until it's required.
 2018-05-25 11:52:10 -07:00
Megan Wachs bdc4355493 Merge remote-tracking branch 'origin/trigger_enum' into riscv-compliance 2018-05-22 16:27:52 -07:00
Megan Wachs a0e811580a Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-22 16:27:29 -07:00
Tim Newsome b629bbeade Delay trigger enumeration until it's required. 
This improves startup time, which is important when connecting to
simulators. One problem is that triggers that are set when the debugger
connects are not cleared until enumeration happens. Execution may halt
due to a trigger set by a previous debug session, which could confuse
the user. If this happens, triggers will be instantly enumerated, so it
will only happen once per session.

Change-Id: I3396f713f16980a8b74745a1672fe8b8a2d4abae
 2018-05-22 13:07:25 -07:00
Tim Newsome 41c42bf2df Comment riscv_set_register, register_write_direct 
Fixes #241

Change-Id: Ia199f15106a0bda465d3918d052ddd4d03655031
 2018-05-17 18:01:00 -07:00
Megan Wachs 9a5a5c2dc9 Merge remote-tracking branch 'origin/reset-unexpected-check' into riscv-compliance 2018-05-16 22:29:45 -07:00
Megan Wachs 802c3b4003
riscv: remove unexpected check during reset 
I'm not sure what this check is adding, and it causes problems for implementations that take some time to report that they are halted out of reset (e.g. by executing Debug ROM).
 2018-05-16 22:25:38 -07:00
Megan Wachs efd7260972 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-14 07:31:25 -07:00
Tim Newsome 909c9d4ab2 Conform to OpenOCD style 
Change-Id: I3954a8ac254b460560fa1414c5921777e4005645
 2018-05-03 17:58:44 -07:00
Tim Newsome 487501e761 Merge branch 'riscv' into optimize 
Change-Id: I2693eb05dee72acd2df5d8594c51e9da08ea1cc6
 2018-05-03 16:02:59 -07:00
Tim Newsome 292180fb44
Merge pull request #246 from darius-bluespec/sysbus-bugfix 
Bug fixes for system bus access
 2018-05-01 14:12:48 -07:00
Darius Rad 31494f68a4 Properly retry system bus access if busy error was detected. 2018-05-01 11:45:24 -04:00
Darius Rad cb282e81bc Fix polling for system bus busy. 2018-05-01 11:45:24 -04:00
Tim Newsome b62c014bdc Merge branch 'riscv' into notice_reset 2018-04-30 13:36:06 -07:00
Ryan Macdonald 0ed96e80d3 Fix more style issues 
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
 2018-04-24 14:15:30 -07:00
Ryan Macdonald 9089854b84 Code cleanup from feedback. 2018-04-24 14:01:21 -07:00
Tim Newsome 9a69c1c096 Fix mingw32 build. 
Change-Id: If7a57749ba8c49385a4020ce8d2d8dbb94242122
 2018-04-20 16:28:24 -07:00
Tim Newsome 4593659edf Fix error messages for reset dmi timeouts. 
Change-Id: I00869ba20db6f27415af8e53e7b3e67741bf894d
 2018-04-20 15:10:56 -07:00
Megan Wachs eeac4f7fd4 riscv-compliance: remove whitespace 2018-04-19 10:52:19 -07:00
Megan Wachs debf2b040a riscv-compliance: correct the HALTSUM0/HALTSUM1 checks 2018-04-19 10:36:52 -07:00
Megan Wachs ac953c71c0 riscv-compliance: add dummy comments to appease the linter 2018-04-18 16:15:07 -07:00
Megan Wachs 06fc61f464 riscv-compliance: whitespace 2018-04-18 16:10:41 -07:00
Megan Wachs 3fedb7d97f Merge remote-tracking branch 'origin/riscv' into HEAD 2018-04-18 15:22:38 -07:00
Tim Newsome 005630d24d Use reset timeout to read dmstatus out of reset 
Change-Id: I74cc6a1e006269270c5197994d21523d01206141
 2018-04-18 14:31:00 -07:00
Tim Newsome 69a426038d
Enforce OpenOCD style guide. (#239) 
* Enforce OpenOCD style guide.

Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8

* Fail if `git diff` fails

Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9

* Maybe every line gets its own shell?

Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6

* Maybe this will error properly.

Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9

* Take different approach than merge-base

Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1

* Fix style issues.

Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
 2018-04-18 13:11:08 -07:00
Megan Wachs 8fa81c1f97 riscv-compliance... code that compiles > code that makes linter happy 2018-04-17 16:11:03 -07:00
Megan Wachs 8ce4f787ca riscv-compliance: whitespace cleanup 2018-04-17 16:05:15 -07:00
Megan Wachs 6217f56186 Merge remote-tracking branch 'origin/notice_reset' into riscv-compliance 2018-04-17 15:47:41 -07:00
Megan Wachs 401dcf7a06 riscv-compliance: make sure reset assertion and deassertion actually worked. 2018-04-17 15:47:15 -07:00
Megan Wachs f516825079 riscv-compliance: make sure not to clear DMACTIVE 2018-04-17 14:30:37 -07:00
Megan Wachs aef4888249 riscv-compliance: Fix writing hartsello 2018-04-17 11:55:50 -07:00
Ryan Macdonald e025cb320c Fix style issues. Code cleanup. 2018-04-17 10:47:44 -07:00
Megan Wachs 30e1dbdc6b riscv-compliance: fix compile errors and whitespace 2018-04-17 10:43:36 -07:00
Ryan Macdonald 4f4d5f46f1 Fix build issues 2018-04-17 10:35:32 -07:00
Megan Wachs ef684c2e68 riscv-compliance: Incorporate feedback to make tests make fewer assumptions about hte implementation and properly use OpenOCD functions 2018-04-17 10:28:13 -07:00
Megan Wachs 716c12bcaf riscv: don't supporess errors 2018-04-17 07:57:32 -07:00
Megan Wachs 4c6c4cb078 riscv: Add a TODO note we need to handle hartselhi 2018-04-17 07:53:34 -07:00
Megan Wachs fa99b8e3b1 riscv-compliance: Fix OpenOCD lint checks 2018-04-17 07:49:06 -07:00
Ryan Macdonald 0b027a2854 Code cleanup. Bump debug_defines.h version 2018-04-16 17:20:31 -07:00
Ryan Macdonald 065671b311 Code style cleanup 2018-04-13 11:20:12 -07:00
Megan Wachs ff365173a0 riscv-compliance: fix too-narrow constant 2018-04-12 17:31:23 -07:00
Megan Wachs 2deff1b2c9 riscv: hartsel-> hartsello (not supporting hartselhi yet) 2018-04-12 16:10:45 -07:00
Megan Wachs adf7dd7b5e Merge branch 'riscv' into riscv-compliance 2018-04-12 16:03:54 -07:00
Megan Wachs 7eca2dfe5d Squashed commit of the following: 
commit fb7009fc38
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 16:41:14 2018 -0800

    Make some error messages to be printed once

commit e09dd62229
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 15:30:10 2018 -0800

    Reduce severity of the error messages that are polluting the log

commit 73b6ea55eb
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 13:32:54 2018 -0800

    removed unused variable

commit c3bdcb0c4a
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 18:32:08 2018 -0800

    more R/O checks

commit 353cf212bd
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 14:27:25 2018 -0800

    write progbuf via DMI

commit e73d82e3d6
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 18:47:36 2018 -0800

    add writes to progbuf

commit f97e4b53e4
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 16:20:12 2018 -0800

    Try to zero out ROM
 2018-04-12 15:02:04 -07:00
Ryan Macdonald 1ba3986eb7 More test/SBA RTL debug 2018-04-12 12:26:54 -07:00
Ryan Macdonald a9b8820916 Checkpoint: debugging tests 2018-04-11 18:10:48 -07:00
Ryan Macdonald 50cd4203a5 Fix more style issues with previous commit 2018-04-11 14:41:00 -07:00
Ryan Macdonald 4191505b76 Fix style issues with previous commit 2018-04-11 14:38:51 -07:00
Ryan Macdonald cc98a14839 Added address alignment test, code fixups from review 2018-04-11 14:26:16 -07:00
Tim Newsome 1fda89c3ce Only write hartsel if we're changing it. 
DebugBreakpoint went from 2.94s to 2.74s.

Change-Id: Ia3ab857aea89fb83f0bcdd9a6bb69f256bde13dd
 2018-04-09 15:13:24 -07:00
Ryan Macdonald 836bd7cb69 Fix sign compare compiler error 2018-04-09 11:55:46 -07:00
Ryan Macdonald c2c52c89b1 Fix some build issues 2018-04-09 11:38:41 -07:00
Ryan Macdonald 99f2f5a272 Change #ifdef SIM_ON to be a run-time arg 2018-04-09 11:26:31 -07:00
Ryan Macdonald de329f4004 Fixed style issues in previous commit. 2018-04-09 10:54:21 -07:00
Ryan Macdonald a9b2277574 Add #ifdef to only enable sbbusyerror test in simulation. 2018-04-09 10:51:53 -07:00
Tim Newsome 238b1e9f06 Cache registers while halted. 
This saves us from re-reading s0 before doing just about anything
program buffer related.

Improves DebugBreakpoint from 3.01s to 2.89s. Feels like the improvement
should be larger than that. Maybe my metric isn't very good.

Change-Id: I85e1a1ddbf09006d76c451a32048be7b773dcfe9
 2018-04-06 15:52:40 -07:00
Ryan Macdonald 7c6f6d79bc Fixed more style issues 2018-04-05 17:59:43 -07:00
Tim Newsome 5c0a9a9ee4 Just read abstractcs once when executing a command 
DebugBreakpoint went from 3.41s to 3.05s!

Change-Id: Icfc4ad5fb663b3607bf2027fda744b43be662fc5
 2018-04-05 17:59:07 -07:00
Ryan Macdonald d471fff3db Fixed build issues 2018-04-05 17:57:53 -07:00
Ryan Macdonald ada78cae11 Checkpoint: fix even more code style issues 2018-04-05 16:49:00 -07:00
Ryan Macdonald 8c8bed878c Checkpoint: fix some more code style issues 2018-04-05 16:42:28 -07:00
Ryan Macdonald 761aaeba98 Checkpoint: fix some code style issues 2018-04-05 16:39:33 -07:00
Ryan Macdonald 3bdb8b29a8 Checkpoint: finish debug of tests, working on hitting sbbusyerror case 2018-04-05 16:31:09 -07:00
Ryan Macdonald c5a8e1cf4c Initial commit of tests for SBA feature 2018-04-04 13:50:17 -07:00
Tim Newsome 6030644a9d Track misa per-hart even in -rtos mode 
This works around some side effects of the -rtos hack, namely that we
were unable to set hardware breakpoints on harts whose misa differed
from the first one. There may be other bugs like this one lurking
elsewhere. The only proper solution is for gdb to have a better user
interface when talking to a server that exposes multiple targets, but
that's a very big project.

This fixes #194.

Change-Id: I81aedddeaa922d220e936730e9c731545953ae21
 2018-04-03 15:12:19 -07:00
Tim Newsome 755c6a4caa Add wall clock timeout to dmi_op() 
If the target is held in reset we'd keep adding more delays, and since
those grow exponentially they'd get so huge it would take forever to
exit out of the loop.

Change-Id: Ieaab8b124c101fd1b12f81f905a6de22192ac662
 2018-03-30 15:24:16 -07:00
Tim Newsome 4ee7d5373d Fix auth error message. 
Change-Id: I79b72325e9a6b85f8b67df8e9837a54cfce928f0
 2018-03-30 13:21:00 -07:00
Tim Newsome 55e427b72b Don't rely on havereset when deasserting reset. 
This removes the need for the supports_havereset config option as well.

Change-Id: Ic4391ce8c15d15e2ef662d170d483f336e8e8a5e
 2018-03-27 11:31:39 -07:00
Tim Newsome c534a37fc3 Make reset work again for multicore 
Both regular multicore and RTOS hack methods.

Change-Id: I9a0998de0f33ef8a4d163f36ddf01c7675893b3d
 2018-03-23 12:53:24 -07:00
Tim Newsome d7282d0bfe Add set_supports_havereset 
This lets reset work on targets that don't implement havereset.

Change-Id: I09eb20970fac740eb6465541db6e739ae3e6b0d5
 2018-03-22 12:44:15 -07:00
Tim Newsome e5591c2584 Halt the target again if it was reset while halted 
Change-Id: I59707e7b2e1646c312d4eb8e96e9d7dfd1e128c2
 2018-03-20 12:34:17 -07:00
Tim Newsome 52eabbd2a5 Add `riscv set_prefer_sba` 
This allows a user to tell OpenOCD to prefer system bus access for
memory access, which can be useful for testing, or when there really is
a difference in behavior.

Change-Id: I8c2f15b89a2ccdae568c68ee743b75a74f9ad6bd
 2018-03-19 14:09:56 -07:00
Tim Newsome d5b450c508 Fix build, broken by b7c5c5d228. 
Change-Id: Iee55d799e14376ec5079d7db5fc6369e85368212
 2018-03-19 12:56:05 -07:00
Tim Newsome 40e0c5b976 Format error messages. 
Change-Id: I50c21319765e1ead279223466ed02a06ecf6a522
 2018-03-19 12:46:10 -07:00
Tim Newsome b7c5c5d228
Merge pull request #225 from riscv/old_bus2 
Support v0 System Bus Access
 2018-03-19 12:11:28 -07:00
Tim Newsome 4d2d1f7324 Notice when a hart has reset. 
Attempt to notify the user.
Deal correctly with a halted target that is suddenly running.

Change-Id: Ib0e0aa843d1da22df673713687ec884f6af14949
 2018-03-16 15:04:14 -07:00
Tim Newsome fd2759a63d Clear havereset in examine() and deassert_reset(). 
Change-Id: I89f32a44ebd6f3df0d0e2f6b54b111daa6ab06f7
 2018-03-16 15:03:31 -07:00
Tim Newsome 848062d0d1 Propagate errors in more places 
Change-Id: I5a7594d4b44c524537827f403348d0c10814546f
 2018-03-16 15:03:31 -07:00
Tim Newsome 3ddbbd525d
Merge pull request #222 from riscv/dmi_commands 
Add riscv dmi_read/dmi_write commands.
 2018-03-15 11:32:33 -07:00
Tim Newsome 68a6812a41 Use TARGET_PRIxADDR instead of PRIx64. 
Change-Id: Iaf71a2d767ff4876b4cf1c9d546744ec6f97dda2
 2018-03-09 18:02:18 -08:00
Tim Newsome 075610d495 Support v0 system bus access 
This code was submitted at
https://github.com/riscv/riscv-openocd/pull/214. This change
incorporates that code, makes it build, and fixes the style to fit the
OpenOCD style guide.

I have not tested the new code because I don't have a target. It does
not cause any regressions.

Change-Id: Ic3639d822c887bd4a5517f044855fdd9d4e5a46d
 2018-03-09 18:02:18 -08:00
Tim Newsome fd9de02fac
Merge pull request #221 from riscv/reg_running 
Error instead of asserting on reg access failure
 2018-03-07 12:22:33 -08:00
Tim Newsome ddb894edf6 Add riscv dmi_read/dmi_write commands. 
Mostly addresses #207.

Also changed dmi_read() to return an error, and fixed all the call sites
to propagate that error if possible.

Change-Id: Ie6fd1f9e7eb46ff92cdb5021a7311ea7334904f1
 2018-03-06 12:45:55 -08:00
Tim Newsome 509e0e4715 Error instead of asserting on reg access failure 
Instead of asserting, return error when an abstract register access
fails on running target.

Fixes #201

Change-Id: I1ab3b31b0a4babf83c44f95ee2eeca92ef906d2f
 2018-03-02 20:24:58 -08:00
Tim Newsome 84c0fdd5d1 Don't always error if a debug program fails 
This is often expected, and the calling code should decide whether to
emit an error or not.

Change-Id: Ic21f38b4c75f01e6b40034fdc60dde6ba7a55f4a
 2018-03-02 20:02:32 -08:00
Tim Newsome 1d00d03dc0 Remove unable to read register error message 
It confuses users of IDEs like Eclipse, which request to read registers
that don't exist on the target.

Fixes #176

Change-Id: Ie2504140bfc70eba0d88fd763aacd87895aa20ff
 2018-03-02 19:41:31 -08:00
Tim Newsome 0c8235d11f
Merge pull request #216 from kaspar030/fix_some_fallthroughs 
target/riscv: add some switch fallthrough comments
 2018-02-28 12:31:22 -08:00
Tim Newsome d388f1cbb2
Merge pull request #218 from riscv/auth 
Add `riscv authdata_read` and `riscv authdata_write` commands to support arbitrary authentication through TCL scripts
 2018-02-28 09:20:31 -08:00
Tim Newsome 39716b15ab Fix authentication for multi-core targets. 
When authdata_write sets the authenticated bit, examine() every OpenOCD
target that is connected to the DM that we were authenticated to.

Change-Id: I542a1e141e2bd23d085e507069a6767e66a196cd
 2018-02-27 14:22:06 -08:00
Tim Newsome 10108b623d Add `authdata_read` and `authdata_write` commands. 
They can be used to authenticate to a Debug Module.

There's a bit of a chicken and egg problem here, because the RISCV
commands aren't available until the target is initialized, but
initialization involves examine(), which can't interact with the target
until authentication has happened. So to use this you run `init`, which
will print out an error, and then run the `riscv authdata_read` and
`riscv authdata_write` commands. When authdata_write() notices that the
authenticated bit went high, it will call examine() again.

Example usage (very simple challenge-response protocol):
```
init

set challenge [ocd_riscv authdata_read]
riscv authdata_write [expr $challenge + 1]

reset halt
```

Change-Id: Id9ead00a7eca111e5ec879c4af4586c30af51f4d
 2018-02-27 09:27:00 -08:00
Tim Newsome 9033d99491
Merge pull request #217 from riscv/disable_target64 
build with --disable-target64
 2018-02-26 12:06:47 -08:00
Tim Newsome 3c1c6e059c
Merge pull request #203 from riscv/sysbusbits 
Add support for system bus master, and for targets that don't have any program buffer
 2018-02-20 09:22:22 -08:00
Kaspar Schleiser d570f89303 target/riscv: add some switch fallthrough comments 2018-02-20 14:31:31 +01:00
Tim Newsome 6b02ab4196 Fix build with --disable-target64 
Change-Id: I5acf47845ff197a1aeb31356de7e4cd8ce63d476
 2018-02-19 15:07:10 -08:00
Tim Newsome 352e6b82ed
Merge pull request #208 from riscv/run_from_trigger 
Handle resuming from a trigger...
 2018-02-19 13:42:50 -08:00
Megan Wachs 1b37f60969 riscv-compliance: Check that DPC is sign extended properly. 2018-02-13 15:02:31 -08:00
Megan Wachs 8f7195af76 riscv-compliance: Turn off ABSTRACTAUTO until the appropriate time 2018-02-13 13:47:14 -08:00
Megan Wachs 313885cb3b riscv-compliance: whitespace fixes 2018-02-13 13:08:15 -08:00
Megan Wachs 2e525e391f riscv-compliance: get it compiling against riscv branch again 2018-02-13 13:01:56 -08:00
Megan Wachs 88370b3989 riscv-compliance: fix some macros which were renamed 2018-02-13 11:44:53 -08:00
Megan Wachs f3bce93dc8 Merge remote-tracking branch 'origin/riscv' into HEAD 2018-02-13 10:57:32 -08:00
Gleb Gagarin 5c543ee3a1 complete reset before writing to hartsel field 2018-02-07 16:06:02 -08:00
Tim Newsome ace6b7e49a Handle resuming from a trigger... 
... by disabling all triggers, single stepping, enabling them, and then
resuming as usual. Without this change, you'd just be stuck on an
address trigger and would have to manually disable it.

Change-Id: I5834984671baa6b64f72e533c4aa94555c64617e
 2018-02-07 13:30:23 -08:00
Megan Wachs 5cf705d360 Merge remote-tracking branch 'origin/riscv' into HEAD 2018-02-06 10:26:22 -08:00
Tim Newsome a80ab87efd Add unreachable return for mingw build. 
Change-Id: I8c0c4d7be8f6f28638cc2b5ae8114f5c8f95f94b
 2018-01-31 16:55:43 -08:00
Tim Newsome 7114ef485c Fix cut and paste bug. 
Change-Id: I1c554cbe3d7cb7845bc62f14ae6b8dff107eb192
 2018-01-31 16:45:33 -08:00
Tim Newsome bb2c25c5ce Make OpenOCD work when there is no program buffer. 
Fixed abstract register access for registers that aren't XLEN wide.
Avoided excessive errors cases where we attempted to execute a fence but
failed.
Don't mark all the CSRs as caller-save. gdb was saving/restoring
dscratch, which broke function calls as a side effect. dscratch is
accessible for people who really know what they're doing, but gdb should
never quietly access it. The same is probably true for other CSRs.

Change-Id: I7bcdbbcb7e3c22ad92cbc205bf537c1fe548b160
 2018-01-31 15:33:45 -08:00
Tim Newsome 6f0d70f5c8 Mention register name instead of number in error 
Change-Id: I5be5e57418e672fc76383fc24635cdbfb1e65578
 2018-01-30 12:30:39 -08:00
Tim Newsome ee93a9b2f1 Add error handling code to system bus read/write 
It's not tested because spike never reports any busy errors since every
access happens instantaneously.

Change-Id: If43ea233a99f98cd419701dc98f0f4a62aa866eb
 2018-01-30 08:53:46 -08:00
Tim Newsome 0f0c5b1ff5 Merge branch 'riscv' into sysbusbits 
Change-Id: Ib7921c73a4bdd586703031be3509d1dec9bb3913
 2018-01-29 11:39:14 -08:00
Tim Newsome 6a98fb7076 Detect hartsellen, limiting which harts we probe 
Tested with doctored spike with hartsellens of 0, 1, 3, and 10.

Change-Id: I97f57c7d03b076792d5ecd66545d9b9e853ed515
 2018-01-26 16:39:58 -08:00
Tim Newsome 5184c32125 Clear errors that we see. 
Also WIP towards handling busy errors, but I'm putting that on hold
while I change the spec...

Change-Id: Iccf47048da46e75b0d769e56004fd783bba1dbf0
 2018-01-26 15:43:05 -08:00
Tim Newsome b67379700b Add support for v1 system bus access. 
This is functional, but doesn't handle errors.

Change-Id: Ifb46af1b0b567f3c2a6135b2ad5eb7ba63a3f595
 2018-01-26 15:43:05 -08:00
Tim Newsome 2d263bae84 Make all memory logging lines consistent. 
Also reduce a few 64-bit variables to 32 bits, which is all they need.

Change-Id: I23e431b7eed4a63803add93a1bb328a3631631d6
 2018-01-24 13:53:11 -08:00
Tim Newsome 42e601afc1
Merge pull request #191 from riscv/scanbuild 
Fix some niggles found by clang's static analysis.
 2018-01-24 07:59:47 -08:00
Tim Newsome 553a63808c Fix some niggles found by clang's static analysis. 
Change-Id: Id476227e1bd02e067f0cc4da9bc7ffb3d9d30535
 2018-01-23 15:16:23 -08:00
Tim Newsome 3839cbf0ad Add some error checking to examine(). 
Fixes #183.

Change-Id: I6fb45adf4c97ea339c9d4ca3b372a09b18e3b56e
 2018-01-19 13:58:02 -08:00
Tim Newsome 7f368468c8 Remove dead code. 
Change-Id: Ic90598b3dd4128dabb18ac4dc1285ca721a6a441
 2018-01-15 12:07:20 -08:00
Tim Newsome 0d60a29c21
Merge pull request #178 from riscv/cleanup 
Rename dummy variable to be correct.
 2018-01-10 15:16:40 -08:00
Tim Newsome 29c7a76708 Muck with mstatus to always be able to read FPRs 
Change-Id: I7ff8bde4578c9ddd175c5cca370295c790cfbba7
 2018-01-09 12:06:11 -08:00
Tim Newsome fd506fa839 Propagate register read errors. 
Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
 2018-01-08 11:53:02 -08:00
Tim Newsome 37434ffd77 Rename dummy variable to be correct. 
Change-Id: I329404894227bb3cf563382e1adf0edda702543b
 2018-01-05 13:05:33 -08:00
Tim Newsome 097d62d159 Make delay update messages debug instead of info. 
They confuse users otherwise.

Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
 2018-01-04 13:36:53 -08:00
Tim Newsome 365c79c3ff Get rid of abort() calls. 
Also changed a few asserts that could trigger due to broken hardware.

Fixes Issue #142.

Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
 2017-12-27 13:45:50 -08:00
Tim Newsome 06445f5743 Propagate error instead of calling abort(). 
As part of this I improved the memory read/write fatal error handling a
bit. Now at least we try to leave autoexec turned off, and will even
restore the temp registers if the situation isn't too hosed for that.

Partly addresses Issue #142

Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
 2017-12-26 15:04:02 -08:00
Tim Newsome d942bce996 Conform to OpenOCD style guide. 
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
 2017-12-26 11:38:11 -08:00
Tim Newsome 56ad0e5b30 Avoid another assertion failure. 
Change-Id: Ia54f778152974164697b712c360918e17a127d95
 2017-12-19 10:41:48 -08:00
Tim Newsome 10c17fdf17 Read misa before using it to check for extensions. 
Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
 2017-12-19 10:41:48 -08:00
Tim Newsome ec1c814017 Don't rely on hart count until it's correct. 
Change-Id: I4e05eb091823b2e0fb481ca0b599072ba1ca70f2
 2017-12-19 10:41:48 -08:00
Tim Newsome 120477b2a2 Simplify examine() 
Now we don't have to play tricks fooling other parts of our code that
might assert.

Change-Id: Ia574378e1f95ed62d297e6b2e852245e58c9ffc9
 2017-12-19 10:41:48 -08:00
Tim Newsome f341db9f72 WIP xml register for 0.11. 
On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.

Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
 2017-12-19 10:41:48 -08:00
Tim Newsome 8926e66d3a Hide unknown registers, which probably don't exist 
Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
 2017-12-19 10:41:48 -08:00
Tim Newsome 26a54452d2 Fix register names. 
Use the ABI ones for every register that we have one for.

Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
 2017-12-19 10:41:48 -08:00
Tim Newsome 7c989698a1 WIP better CSR names, and include only existing 
Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
 2017-12-19 10:41:48 -08:00
Tim Newsome a5cb0b2270 WIP. Hide FPRs if the hart doesn't support F/D. 
Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
 2017-12-19 10:41:48 -08:00