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12260 Commits

Author SHA1 Message Date
Miodrag Milanovic f790e00478 Next dev cycle 2023-05-09 08:00:06 +02:00
Miodrag Milanovic 9c5a60eb20 Release version 0.29 2023-05-09 07:57:55 +02:00
github-actions[bot] 0469405abf Bump version 2023-05-09 00:15:34 +00:00
N. Engelhardt 266036c6f9
Merge pull request #3756 from YosysHQ/krys/sim_writeback 2023-05-08 16:21:24 +02:00
N. Engelhardt 0aeb6105eb
Merge pull request #3736 from jix/conc_assertion_in_unclocked_proc_ctx 2023-05-08 16:15:13 +02:00
N. Engelhardt ec56e625f4
Merge pull request #3742 from jix/fix_rename_witness_cell_renames 2023-05-08 16:13:28 +02:00
Krystine Sherwin 5a4e72f57a
Fix sim writeback check for yw_cosim 
Writeback of simulation state into initial state was only working for `run()` and `run_cosim_fst()`.
This change moves the writeback into the `write_output_files()` function so that all simulation modes work with the writeback option.
 2023-05-08 13:13:09 +12:00
Miodrag Milanović 4251d37f4f
Merge pull request #3610 from YosysHQ/synthprop 
Synthesizable properties
 2023-05-05 11:03:09 +02:00
github-actions[bot] f93671eb85 Bump version 2023-05-05 00:15:06 +00:00
Jannis Harder 32f5fca2aa
Merge pull request #3694 from daglem/struct-attributes 
Handling of attributes for struct / union variables
 2023-05-04 22:15:10 +02:00
Dag Lem fb7f3bb290 Cleaner tests for RTLIL cells in struct_dynamic_range.sv 2023-05-04 14:28:21 +02:00
Dag Lem ad437c178d Handling of attributes for struct / union variables 
(* nowrshmsk *) on a struct / union variable now affects dynamic
bit slice assignments to members of the struct / union.

(* nowrshmsk *) can in some cases yield significant resource savings; the
combination of pipeline shifting and indexed writes is an example of this.

Constructs similar to the one below can benefit from (* nowrshmsk *), and
in addition it is no longer necessary to split out the shift assignments
on separate lines in order to avoid the error message "ERROR: incompatible
mix of lookahead and non-lookahead IDs in LHS expression."

    always_ff @(posedge clk) begin
        if (rotate) begin
            { v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 };

            if (res) begin
                v0.bytes <= '0;
            end else if (w) begin
                v0.bytes[addr] <= data;
            end
        end
    end
 2023-05-03 18:44:07 +02:00
Jannis Harder 7bff8b63b3 rename: Fix renaming cells in -witness mode 
This was renaming cells while iterating over them which would always
cause an assertion failure. Apparently having to rename cells to make
all witness signals public is rarely required, so this slipped through.
 2023-04-25 12:39:00 +02:00
Jannis Harder cee3cb31b9
Merge pull request #3734 from jix/fix_unbased_unsized_const 
verilog: Fix const eval of unbased unsized constants
 2023-04-24 16:08:48 +02:00
github-actions[bot] 51dd029024 Bump version 2023-04-23 00:17:11 +00:00
Benjamin Barzen 8611429237
ABC9: Cell Port Bug Patch (#3670) 
* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2023-04-22 16:24:36 -07:00
Jannis Harder 3cbca5064c verific: Handle non-seq properties with VerificClocking conditions 2023-04-21 17:19:42 +02:00
Jannis Harder ec47bf1745 verific: Handle conditions when using sva_at_only in VerificClocking 
This handles conditions on clocked concurrent assertions in unclocked
procedural contexts.
 2023-04-21 16:51:42 +02:00
Jannis Harder 985f4926b7 verilog: Fix const eval of unbased unsized constants 
When the verilog frontend perfomed constant evaluation of unbased
unsized constants in a context-determined expression it did not properly
extend them by repeating the bit value. This only affected constant
evaluation and not constants that made it through unchanged to RTLIL.
The latter case was already covered by tests and working before.

This fixes the const-eval issue by checking the `is_unsized` flag in
bitsAsConst and extending the value accordingly.

The newly added test also tests the already working non-const-eval case
to highlight that both cases should behave the same.
 2023-04-20 12:12:50 +02:00
github-actions[bot] 7efc50367e Bump version 2023-04-19 00:16:35 +00:00
Jannis Harder 88ae463ffe
Merge pull request #3732 from hzeller/20230417-remote-statement-no-effect 
Remove a statement without effect.
 2023-04-18 10:45:14 +02:00
Henner Zeller a3a8f7be38 Remove a statement without effect. 
The return value of the min(...) call is never used.
Looks like some leftover from some previous implementation.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
 2023-04-17 10:53:05 -07:00
github-actions[bot] a9c792dcee Bump version 2023-04-15 00:16:41 +00:00
Miodrag Milanovic d0855576ae Next dev cycle 2023-04-14 09:54:46 +02:00
Miodrag Milanovic 0d6f4b0683 Release version 0.28 2023-04-14 09:52:15 +02:00
Miodrag Milanović b377a39b73
Merge pull request #3727 from YosysHQ/micko/pll_bram 
MachXO2: Add PLL and EBR related primitives
 2023-04-14 09:34:30 +02:00
github-actions[bot] a2655a4b70 Bump version 2023-04-13 00:14:37 +00:00
gatecat e56dad56c4 fabulous: Add support for LUT6s 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-12 18:42:09 +02:00
YRabbit f9a6c0fcbd gowin: Add serialization/deserialization primitives 
Primitives are added to convert parallel signals to serial and vice versa.

IDES4, IDES8, IDES10, IDES16, IVIDEO, OSER4, OSER8, OSER10, OSER16, OVIDEO.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-12 09:59:57 +01:00
Miodrag Milanovic ee3162c58d Add PLL and EBR related primitives 2023-04-10 12:39:09 +02:00
github-actions[bot] 101075611f Bump version 2023-04-07 00:14:38 +00:00
gatecat 266f81816b ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-06 10:18:48 +01:00
Miodrag Milanovic 0f5e7c244d add additional dff and lutram tests 2023-04-06 09:10:14 +02:00
Miodrag Milanovic 54d313efc3 add test for CCU2D 2023-04-06 09:10:14 +02:00
Miodrag Milanovic 9e9fae1966 Add more DFF types 2023-04-06 09:10:14 +02:00
Miodrag Milanovic d5a405d3b4 Added proper simulation model for CCU2D 2023-04-06 09:10:14 +02:00
Miodrag Milanovic 6e4c1675e7 Generate TRELLIS_DPR16X4 for lutram 2023-04-06 09:10:14 +02:00
Miodrag Milanovic 6e12da3956 machxo2: Initial support for carry chains (CCU2D) 2023-04-06 09:10:14 +02:00
github-actions[bot] 53c0a6b780 Bump version 2023-03-24 00:16:02 +00:00
Miodrag Milanovic f35bdaa527 Update Xilinx cell definitions, fixes #3699 2023-03-23 09:44:36 +01:00
github-actions[bot] 23826e5152 Bump version 2023-03-21 00:15:46 +00:00
Jannis Harder dc0a799c06
Merge pull request #3708 from jix/void_func 
verilog: Support void functions
 2023-03-20 16:10:19 +01:00
Jannis Harder fb1c2be76b verilog: Support void functions 
The difference between void functions and tasks is that always_comb's
implicit sensitivity list behaves as if functions were inlined, but
ignores signals read only in tasks. This only matters for event based
simulation, and for synthesis we can treat a void function like a task.
 2023-03-20 12:52:46 +01:00
Miodrag Milanovic 61da330a38 Update tests 2023-03-20 09:58:41 +01:00
Miodrag Milanovic ff9f1fb86e Start unification effort for machxo2 and ecp5 2023-03-20 09:58:41 +01:00
Miodrag Milanovic 4d7e9e2e5d Add additional iopad_external_pin attributes 2023-03-20 09:17:22 +01:00
Miodrag Milanovic db367bd69e Add iopad_external_pin to some basic io primitives 2023-03-20 09:17:22 +01:00
Miodrag Milanovic 10589c57bf insert IO buffers for ECP5, off by default 2023-03-20 09:17:22 +01:00
github-actions[bot] ceef00c35e Bump version 2023-03-16 00:17:57 +00:00
Miodrag Milanović 57fb1f51b2
Merge pull request #3704 from jix/enum_values 
verific: Fix enum_values support and signed attribute values
 2023-03-15 10:54:19 +01:00