mirror of https://github.com/YosysHQ/yosys.git
Cleaner tests for RTLIL cells in struct_dynamic_range.sv
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@ -1,4 +1,3 @@
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/*.log
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/*.out
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/run-test.mk
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/temp
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@ -1,8 +1,7 @@
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! mkdir -p temp
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read_verilog -sv struct_dynamic_range.sv
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write_rtlil temp/struct_dynamic_range.il
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! grep -F -q ' cell $shift ' temp/struct_dynamic_range.il
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! grep -F -q ' switch $mul' temp/struct_dynamic_range.il
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select -assert-count 4 t:$mul
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select -assert-count 2 t:$shift
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select -assert-count 2 t:$shiftx
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prep -top top
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flatten
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sat -enable_undef -verify -prove-asserts
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