riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
12,260 Commits 81 Branches 48 Tags 64 MiB
Commit Graph

12260 Commits

Author SHA1 Message Date
Jannis Harder 390d1c583a verific: Fix enum_values support and signed attribute values 
This uses the same constant parsing for enum_values and for attributes
and extends it to handle signed values as those are used for enums that
implicitly use the int type.
 2023-03-15 09:51:36 +01:00
github-actions[bot] 101d19bb6a Bump version 2023-03-11 00:15:30 +00:00
Jannis Harder c50f641812
Merge pull request #3682 from daglem/struct-member-out-of-bounds 
Out of bounds checking for struct/union members
 2023-03-10 16:14:56 +01:00
Stefan Riesenberger baa3659ea5 ice40: Fix path delay definitions 
Parallel connections do not allow matching different bit widths.
A full connection has to be used instead.
Allows iverilog to parse the simulation library with hardware path delays enabled.
 2023-03-10 10:48:05 +01:00
Dag Lem 1af7d6121f Added test for dynamic indexing within struct members 2023-03-08 20:25:39 +01:00
github-actions[bot] b58664d441 Bump version 2023-03-07 00:18:51 +00:00
N. Engelhardt 7c5ae560a8
Merge pull request #3684 from YosysHQ/fix-GIT_REV 2023-03-06 16:12:36 +01:00
Miodrag Milanovic 368f2984cd Next dev cycle 2023-03-06 08:50:14 +01:00
Miodrag Milanovic 5f88c218b5 Release version 0.27 2023-03-06 08:47:51 +01:00
Dag Lem 0d3423ddea Index struct/union members within corresponding wire chunks 
This guards against access to bits outside of struct/union
members via dynamic indexing.
 2023-03-05 14:54:17 +01:00
github-actions[bot] 9747e55d95 Bump version 2023-03-02 00:18:47 +00:00
Catherine 3f173c2180 Makefile: fix GIT_REV extraction if Yosys is built as submodule. 2023-03-01 21:17:19 +00:00
N. Engelhardt 981c934b5b
Merge pull request #3690 from whitequark/smtbmc-help-opt 2023-03-01 09:59:01 +01:00
N. Engelhardt 25ebefc2a6
Merge pull request #3692 from nakengelhardt/stat_q_fix 2023-03-01 09:49:36 +01:00
N. Engelhardt 1a3ff0d926
Merge pull request #3688 from pu-cc/gatemate-reginit 2023-03-01 09:49:14 +01:00
N. Engelhardt 57897927ff stat: pass down quiet arg 2023-02-28 17:12:55 +01:00
Miodrag Milanović bb28e48136
Merge pull request #3663 from uis246/master 
gowin: Add new types of oscillator
 2023-02-28 06:56:01 +01:00
Miodrag Milanović 4ff9063145
Merge pull request #3652 from martell/elvds 
gowin: Add support for emulated differential output
 2023-02-28 06:55:25 +01:00
github-actions[bot] 71c59d9fab Bump version 2023-02-28 00:17:33 +00:00
Catherine 4bb173e256 yosys-smtbmc: support -h/--help (and exit with code 0). 2023-02-27 20:31:00 +00:00
Miodrag Milanović 21e87f7986
Merge pull request #3646 from YosysHQ/lofty/fix-3591 
muxcover: do not add decode muxes with x inputs
 2023-02-27 16:26:57 +01:00
N. Engelhardt 842cdad575
Merge pull request #3674 from YosysHQ/fix_wide_case 2023-02-27 16:04:11 +01:00
gatecat 2ab3747cc9 fabulous: Add support for mapping carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-27 09:50:34 +01:00
Miodrag Milanovic 28c4aac234 run verific tests in test target 2023-02-27 09:27:04 +01:00
Miodrag Milanovic d8cefec169 Added ranged case check 2023-02-27 09:24:04 +01:00
Miodrag Milanovic 53a4f0fb56 Add test example 2023-02-27 09:24:04 +01:00
Miodrag Milanovic a30894e5fa Handle more wide case selector types 2023-02-27 09:24:04 +01:00
github-actions[bot] 8216b23fb7 Bump version 2023-02-24 00:16:59 +00:00
Catherine ef8ed21a2e
Merge pull request #3685 from YosysHQ/update-abc 
Update abc
 2023-02-23 07:57:27 +00:00
Catherine 5d9bd0af92 Update abc. 2023-02-23 01:48:21 +00:00
github-actions[bot] 0f2d226ae9 Bump version 2023-02-21 00:17:40 +00:00
N. Engelhardt c8966722d2
Merge pull request #3403 from KrystalDelusion/mem-tests 2023-02-20 18:27:24 +01:00
KrystalDelusion f80920bd9f Genericising bug1836.ys 2023-02-21 05:23:16 +13:00
KrystalDelusion 445a801a85 bug3205.ys removed 
Made redundant by TDP test(s) in memories.ys
 2023-02-21 05:23:16 +13:00
KrystalDelusion 51c2d476c2 Removing extra `default_nettype` lines 2023-02-21 05:23:16 +13:00
KrystalDelusion 8f6a06951c Fix for sync_ram_sdp not being final module 
Explicitly declare -top in synth_intel_alm.
 2023-02-21 05:23:16 +13:00
KrystalDelusion 7f033d3c1f More tests in memlib/generate.py 
Covers most of the todo list, at least functionally.  Some minor issues with not always using hardware features.
 2023-02-21 05:23:15 +13:00
KrystalDelusion af1b9c9e07 Tests for ram_style = "huge" 
iCE40 SPRAM and Xilinx URAM
 2023-02-21 05:23:15 +13:00
KrystalDelusion de2f140c09 Testing TDP synth mapping 
New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.
 2023-02-21 05:23:15 +13:00
KrystalDelusion 48f4e09202 Asymmetric port ram tests with Xilinx 
Uses verilog code from User Guide 901 (2021.1)
 2023-02-21 05:23:14 +13:00
KrystalDelusion ac5fa9a838 Addings tests for #1836 and #3205 2023-02-21 05:23:14 +13:00
Dag Lem 79043cb849 Out of bounds checking for struct/union members 
Currently, only constant indices are checked.
 2023-02-19 23:25:08 +01:00
github-actions[bot] f0116330bc Bump version 2023-02-18 00:17:33 +00:00
N. Engelhardt f30b539cc2
Merge pull request #3681 from keszocze/keszocze-patch-dsp48e1-init-dreg 2023-02-17 18:40:22 +01:00
Oliver Keszöcze fc56978703
Check DREG attribute 
The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
 2023-02-17 17:54:41 +01:00
github-actions[bot] 1cfedc90ce Bump version 2023-02-17 00:18:18 +00:00
gatecat 25e7cb3bbb fabulous: Add CLK to BRAM interface primitives 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-16 12:55:53 +01:00
github-actions[bot] a20804c6ed Bump version 2023-02-16 00:17:37 +00:00
Patrick Urban 2c7ba0e752 gatemate: Enable register initialization 2023-02-15 17:29:01 +01:00
Jannis Harder 1c667fab2b
Merge pull request #3672 from jix/yw-cosim-hierarchy-fixes 
sim: For yw cosim, drive parent module's signals for input ports
 2023-02-15 13:45:00 +01:00