mirror of https://github.com/YosysHQ/yosys.git
ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model
Signed-off-by: gatecat <gatecat@ds0.me>
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gatecat
Lofty
parent
0f5e7c244d
commit
266f81816b
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@ -413,177 +413,47 @@ endmodule
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// ---------------------------------------
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module TRELLIS_SLICE(
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input A0, B0, C0, D0,
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input A1, B1, C1, D1,
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input M0, M1,
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input FCI, FXA, FXB,
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input CLK, LSR, CE,
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input DI0, DI1,
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input WD0, WD1,
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module TRELLIS_COMB(
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input A, B, C, D, M,
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input FCI, F1, FXA, FXB,
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input WD,
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input WAD0, WAD1, WAD2, WAD3,
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input WRE, WCK,
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output F0, Q0,
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output F1, Q1,
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output FCO, OFX0, OFX1,
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output WDO0, WDO1, WDO2, WDO3,
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output WADO0, WADO1, WADO2, WADO3
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output F, FCO, OFX
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);
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parameter MODE = "LOGIC";
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parameter GSR = "ENABLED";
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parameter SRMODE = "LSR_OVER_CE";
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parameter [127:0] CEMUX = "1";
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parameter CLKMUX = "CLK";
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parameter LSRMUX = "LSR";
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parameter LUT0_INITVAL = 16'h0000;
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parameter LUT1_INITVAL = 16'h0000;
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parameter REG0_SD = "0";
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parameter REG1_SD = "0";
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parameter REG0_REGSET = "RESET";
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parameter REG1_REGSET = "RESET";
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parameter REG0_LSRMODE = "LSR";
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parameter REG1_LSRMODE = "LSR";
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parameter [127:0] CCU2_INJECT1_0 = "NO";
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parameter [127:0] CCU2_INJECT1_1 = "NO";
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parameter INITVAL = 16'h0;
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parameter CCU2_INJECT1 = "NO";
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parameter WREMUX = "WRE";
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parameter WCKMUX = "WCK";
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parameter A0MUX = "A0";
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parameter A1MUX = "A1";
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parameter B0MUX = "B0";
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parameter B1MUX = "B1";
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parameter C0MUX = "C0";
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parameter C1MUX = "C1";
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parameter D0MUX = "D0";
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parameter D1MUX = "D1";
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wire A0m, B0m, C0m, D0m;
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wire A1m, B1m, C1m, D1m;
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parameter IS_Z1 = 1'b0;
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generate
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if (A0MUX == "1") assign A0m = 1'b1; else assign A0m = A0;
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if (B0MUX == "1") assign B0m = 1'b1; else assign B0m = B0;
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if (C0MUX == "1") assign C0m = 1'b1; else assign C0m = C0;
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if (D0MUX == "1") assign D0m = 1'b1; else assign D0m = D0;
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if (A1MUX == "1") assign A1m = 1'b1; else assign A1m = A1;
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if (B1MUX == "1") assign B1m = 1'b1; else assign B1m = B1;
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if (C1MUX == "1") assign C1m = 1'b1; else assign C1m = C1;
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if (D1MUX == "1") assign D1m = 1'b1; else assign D1m = D1;
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endgenerate
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function [15:0] permute_initval;
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input [15:0] initval;
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integer i;
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begin
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for (i = 0; i < 16; i = i + 1) begin
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permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i];
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end
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end
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endfunction
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generate
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if (MODE == "LOGIC") begin
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// LUTs
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LUT4 #(
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.INIT(LUT0_INITVAL)
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) lut4_0 (
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.A(A0m), .B(B0m), .C(C0m), .D(D0m),
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.Z(F0)
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);
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LUT4 #(
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.INIT(LUT1_INITVAL)
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) lut4_1 (
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.A(A1m), .B(B1m), .C(C1m), .D(D1m),
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.Z(F1)
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);
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// LUT expansion muxes
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PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0));
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L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
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end else if (MODE == "CCU2") begin
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CCU2C #(
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.INIT0(LUT0_INITVAL),
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.INIT1(LUT1_INITVAL),
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.INJECT1_0(CCU2_INJECT1_0),
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.INJECT1_1(CCU2_INJECT1_1)
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) ccu2c_i (
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.CIN(FCI),
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.A0(A0m), .B0(B0m), .C0(C0m), .D0(D0m),
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.A1(A1m), .B1(B1m), .C1(C1m), .D1(D1m),
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.S0(F0), .S1(F1),
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.COUT(FCO)
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);
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end else if (MODE == "RAMW") begin
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assign WDO0 = C1m;
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assign WDO1 = A1m;
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assign WDO2 = D1m;
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assign WDO3 = B1m;
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assign WADO0 = D0m;
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assign WADO1 = B0m;
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assign WADO2 = C0m;
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assign WADO3 = A0m;
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end else if (MODE == "DPRAM") begin
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TRELLIS_RAM16X2 #(
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.INITVAL_0(permute_initval(LUT0_INITVAL)),
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.INITVAL_1(permute_initval(LUT1_INITVAL)),
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.WREMUX(WREMUX)
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) ram_i (
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.DI0(WD0), .DI1(WD1),
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.WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
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.WRE(WRE), .WCK(WCK),
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.RAD0(D0m), .RAD1(B0m), .RAD2(C0m), .RAD3(A0m),
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.DO0(F0), .DO1(F1)
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);
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// TODO: confirm RAD and INITVAL ordering
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// DPRAM mode contract?
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`ifdef FORMAL
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always @(*) begin
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assert(A0m==A1m);
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assert(B0m==B1m);
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assert(C0m==C1m);
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assert(D0m==D1m);
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end
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`endif
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if (MODE == "LOGIC") begin: mode_logic
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LUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F));
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end else if (MODE == "CCU2") begin: mode_ccu2
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wire l4o, l2o;
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LUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o));
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LUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o));
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wire gated_cin_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : FCI;
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assign F = l4o ^ gated_cin_0;
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wire gated_lut2_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : l2o;
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wire FCO = (~l4o & gated_lut2_0) | (l4o & FCI);
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end else if (MODE == "DPRAM") begin: mode_dpram
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reg [15:0] ram = INITVAL;
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always @(posedge WCK)
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if (WRE)
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ram[{WAD3, WAD2, WAD1, WAD0}] <= WD;
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assign F = ram[{A, C, B, D}];
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end else begin
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ERROR_UNKNOWN_SLICE_MODE error();
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$error("unsupported COMB mode %s", MODE);
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end
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if (IS_Z1)
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L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX));
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else
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PFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX));
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endgenerate
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// FF input selection muxes
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wire muxdi0 = (REG0_SD == "1") ? DI0 : M0;
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wire muxdi1 = (REG1_SD == "1") ? DI1 : M1;
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// Flipflops
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TRELLIS_FF #(
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.GSR(GSR),
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.CEMUX(CEMUX),
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.CLKMUX(CLKMUX),
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.LSRMUX(LSRMUX),
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.SRMODE(SRMODE),
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.REGSET(REG0_REGSET),
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.LSRMODE(REG0_LSRMODE)
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) ff_0 (
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.CLK(CLK), .LSR(LSR), .CE(CE),
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.DI(muxdi0), .M(M0),
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.Q(Q0)
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);
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TRELLIS_FF #(
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.GSR(GSR),
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.CEMUX(CEMUX),
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.CLKMUX(CLKMUX),
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.LSRMUX(LSRMUX),
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.SRMODE(SRMODE),
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.REGSET(REG1_REGSET),
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.LSRMODE(REG1_LSRMODE)
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) ff_1 (
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.CLK(CLK), .LSR(LSR), .CE(CE),
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.DI(muxdi1), .M(M1),
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.Q(Q1)
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);
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endmodule
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(* blackbox *)
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