Andrew Zonenberg
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ac75524f69
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Fixed undeclared "count" in GP_COUNT8_ADV
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2017-08-14 10:45:39 -07:00 |
Andrew Zonenberg
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db20e3f1c2
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Fixed undeclared "count" in GP_COUNT14_ADV
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2017-08-14 10:45:39 -07:00 |
Andrew Zonenberg
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3618ca2218
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Fixed typo in last commit
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2017-08-14 10:45:39 -07:00 |
Andrew Zonenberg
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4da1a327c0
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Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else.
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2017-08-14 10:45:39 -07:00 |
Andrew Zonenberg
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4504dd78e9
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Fixed typo in COUNT8 model
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2017-08-14 10:45:39 -07:00 |
Andrew Zonenberg
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60dd5dba7b
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Moved GP_POR out of digital cells b/c it has delays
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2017-08-14 10:45:39 -07:00 |
Andrew Zonenberg
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f55d4cc2fd
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Improved cells_sim_digital model for GP_COUNT8
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2017-08-14 10:45:39 -07:00 |
Andrew Zonenberg
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fe3a932cfa
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Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
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2017-08-14 10:45:39 -07:00 |
Andrew Zonenberg
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1bb150c231
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Improved handling of constant connections in opt_rmports
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2017-08-14 10:28:19 -07:00 |
Andrew Zonenberg
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2877d5e504
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Fixed handling of cell ports that aren't wires
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2017-08-14 10:28:16 -07:00 |
Andrew Zonenberg
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3dd7f42e2b
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opt_rmports: Fixed incorrect handling of multi-bit nets
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2017-08-14 10:28:11 -07:00 |
Andrew Zonenberg
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66aac06eee
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Removed commented out debug code
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2017-08-14 10:28:04 -07:00 |
Andrew Zonenberg
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cca3cb5fbb
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Added opt_rmports pass (remove unconnected ports from top-level modules)
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2017-08-14 10:27:59 -07:00 |
Clifford Wolf
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007f29b9c2
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Add support for set-reset cell variants to opt_rmdff
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2017-08-09 13:29:52 +02:00 |
Clifford Wolf
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159701962a
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Auto-detect JSON front-end
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2017-08-09 13:28:52 +02:00 |
Clifford Wolf
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c4a7958f70
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Add handling of constant reset signals to opt_rmdff
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2017-08-06 13:27:18 +02:00 |
Clifford Wolf
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48b2b376d0
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Add "yosys-smtbmc --smtc-init --smtc-top --noinit"
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2017-08-04 17:09:08 +02:00 |
Clifford Wolf
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1dc921d9a1
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Add "-undefined dynamic_lookup" to OSX "yosys-config --ldflags"
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2017-08-04 11:24:58 +02:00 |
Clifford Wolf
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5c09f24e48
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Fix typo in "abc" pass help message
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2017-07-29 16:21:58 +02:00 |
Clifford Wolf
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15073790bf
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Add merging of "past FFs" to verific importer
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2017-07-29 00:10:38 +02:00 |
Clifford Wolf
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e7d1277a2c
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Add consolidation of init attributes to opt_clean, some opt_clean log fixes
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2017-07-29 00:10:33 +02:00 |
Clifford Wolf
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d4b9602cbd
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Add minimal support for PSL in VHDL via Verific
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2017-07-28 17:39:49 +02:00 |
Clifford Wolf
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4cf890dac1
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Add simple VHDL+PSL example
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2017-07-28 17:39:43 +02:00 |
Clifford Wolf
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5a828fff34
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Improve Verific HDL language options
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2017-07-28 15:32:54 +02:00 |
Clifford Wolf
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acd6cfaf67
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Fix handling of non-user-declared Verific netbus
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2017-07-28 11:31:27 +02:00 |
Clifford Wolf
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c1cfca8f54
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Improve Verific SVA importer
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2017-07-27 14:05:09 +02:00 |
Clifford Wolf
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877ff1f75e
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Add counter.sv SVA test
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2017-07-27 12:37:16 +02:00 |
Clifford Wolf
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2336d5508b
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Add log_warning_noprefix() API, Use for Verific warnings and errors
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2017-07-27 12:17:04 +02:00 |
Clifford Wolf
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d9641621d9
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Add "verific -import -n" and "verific -import -nosva"
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2017-07-27 11:54:45 +02:00 |
Clifford Wolf
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b24f737759
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Improve SVA tests, add Makefile and scripts
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2017-07-27 11:42:05 +02:00 |
Clifford Wolf
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90d8329f64
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Improve Verific SVA import: negedge and $past
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2017-07-27 11:40:07 +02:00 |
Clifford Wolf
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147ff96ba3
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Improve Verific SVA importer
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2017-07-27 10:39:39 +02:00 |
Clifford Wolf
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649bb9374f
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Add "opt_expr -fine" feature to remove neutral bits from reduce and logic operators
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2017-07-26 18:28:55 +02:00 |
Clifford Wolf
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530040ba6f
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Improve Verific bindings (mostly related to SVA)
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2017-07-26 18:00:01 +02:00 |
Clifford Wolf
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abd3b4e8e7
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Improve "help verific" message
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2017-07-25 15:13:22 +02:00 |
Clifford Wolf
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6dbe1d4c92
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Add "verific -extnets"
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2017-07-25 14:53:11 +02:00 |
Clifford Wolf
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493fedbaf9
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Add "using std::get" to yosys.h
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2017-07-25 14:52:34 +02:00 |
Clifford Wolf
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c97c92e4ec
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Improve "verific -all" handling
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2017-07-25 13:33:25 +02:00 |
Clifford Wolf
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41be530c4e
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Add "verific -import -d <dump_file"
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2017-07-24 13:57:16 +02:00 |
Clifford Wolf
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92d3aad670
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Add "verific -import -flatten" and "verific -import -v"
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2017-07-24 11:29:06 +02:00 |
Clifford Wolf
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84f15260b5
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Add more SVA test cases for future Verific work
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2017-07-22 16:35:46 +02:00 |
Clifford Wolf
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5be535517c
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Add "verific -import -k"
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2017-07-22 16:16:44 +02:00 |
Clifford Wolf
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b6bd12fade
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Add error for cell output ports that are connected to constants
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2017-07-22 15:08:30 +02:00 |
Clifford Wolf
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024ba310ec
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Add some simple SVA test cases for future Verific work
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2017-07-22 12:31:08 +02:00 |
Clifford Wolf
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2785aaffeb
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Improve docs for verific bindings, add simply sby example
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2017-07-22 11:58:51 +02:00 |
Clifford Wolf
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b3bc7068d1
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Fix handling of empty cell port assignments (i.e. ignore them)
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2017-07-21 19:32:31 +02:00 |
Clifford Wolf
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36cf18ac4c
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Fix "read_blif -wideports" handling of cells with wide ports
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2017-07-21 16:21:12 +02:00 |
Clifford Wolf
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26766da343
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Add a paragraph about pre-defined macros to read_verilog help message
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2017-07-21 14:34:53 +02:00 |
Clifford Wolf
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3a8f6f0f51
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Add verilator support to testbenches generated by yosys-smtbmc
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2017-07-21 14:33:29 +02:00 |
Clifford Wolf
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c251e3a576
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Change intptr_t to uintptr_t in hashlib.h
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2017-07-18 17:38:19 +02:00 |