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103 Commits

Author SHA1 Message Date
Ruben Undheim 436e3c0a7c Refactor code to avoid code duplication + added comments 2018-10-20 16:06:48 +02:00
Ruben Undheim 397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
 2018-10-13 20:34:44 +02:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf 5f2bc1ce76 Add automatic verific import in hierarchy command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-20 23:45:01 +02:00
Clifford Wolf 3ab79a231b Bugfix in handling of array instances with empty ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-31 18:09:31 +02:00
Clifford Wolf 11406a8082 Add "hierarchy -simcheck" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 13:59:13 +02:00
Clifford Wolf ee3c12d6d9 Chenged "extensions_map" to "extensions_list" in hierarchy.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-27 14:12:57 +02:00
Sergi Granell f93f8aaa11 passes/hierarchy: Reduce code duplication in expand_module 
This also makes it easier to add new file extensions support.

Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com>
 2018-03-27 09:35:20 +02:00
Clifford Wolf 491c352da7 Add .sv support to "hierarchy -libdir" 2018-03-26 21:19:00 +02:00
Clifford Wolf 446ccf1f05 Bugfix in hierarchy blackbox module port width handling 2018-01-07 16:35:22 +01:00
Clifford Wolf c80315cea4 Bugfix in hierarchy handling of blackbox module ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-05 13:28:45 +01:00
Clifford Wolf 2d140a44eb Temporarily derive blackbox modules in hierarchy to evaluate port widths 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-04 13:23:29 +01:00
Clifford Wolf ca53fba44a Rename "singleton" pass to "uniquify" 2017-08-20 12:31:50 +02:00
Clifford Wolf b6bd12fade Add error for cell output ports that are connected to constants 2017-07-22 15:08:30 +02:00
Clifford Wolf b3bc7068d1 Fix handling of empty cell port assignments (i.e. ignore them) 2017-07-21 19:32:31 +02:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf 69468d5a16 Do not fix port widths on any blackbox instances 2017-02-13 17:07:38 +01:00
Clifford Wolf 76c4ee096b Do not eagerly fix port widths on parameterized cells 2017-02-12 17:42:57 +01:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Austin Seipp 6781543244 passes/hierarchy: delete some dead code 
Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2017-01-15 16:39:12 -06:00
Clifford Wolf f0df7dd796 Added cell port resizing to hierarchy pass 2017-01-01 23:03:44 +01:00
Clifford Wolf 70d7a02cae Added support for hierarchical defparams 2016-11-15 13:35:19 +01:00
Clifford Wolf 1827a48964 Minor bugfix in submod 2016-11-09 13:13:26 +01:00
Clifford Wolf 308a4b4a1b Bugfix in "hierarchy -check" 2016-11-02 20:09:57 +01:00
Clifford Wolf aa72262330 Added avail params to ilang format, check module params in 'hierarchy -check' 2016-10-22 11:05:49 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 00f29d5e5c Fixed use-after-free dict<> usage pattern in hierarchy.cc 2016-08-16 09:07:13 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Marcus Comstedt e22e4d59b8 Made the expansion order of hierarchy deterministic 2016-05-22 16:41:26 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf 043fa0fad0 Cleanup abstract modules at end of "hierarchy -top" 2016-03-21 16:37:35 +01:00
Clifford Wolf d00c63c927 Added "submod -copy" 2016-01-08 09:08:12 +01:00
Clifford Wolf 1ec6429bad Added "singleton" pass 2015-11-07 19:10:43 +01:00
Clifford Wolf 207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf 2397078485 Keep modules with $assume (like $assert) 2015-07-25 12:09:57 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf c52a4cdeed Added "dffinit", Support for initialized Xilinx DFF 2015-04-04 19:00:15 +02:00
Clifford Wolf 4b44907619 documentation improvements 2015-03-29 20:22:08 +02:00
Clifford Wolf aed4d763cf Added hierarchy -auto-top 2015-03-18 08:33:40 +01:00
Clifford Wolf ed15400fc6 Fixed bug in "hierarchy" for parametric designs 2015-03-04 15:52:34 +01:00
Clifford Wolf a54c994e2b Cosmetic fixes in "hierarchy" for blackbox modules 2015-02-15 12:57:41 +01:00
Clifford Wolf 0648e2874c Fixed pattern matching in "hierarchy -generate" 2015-01-04 11:45:39 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf b6a7e21d2e Fixed off-by-one bug in "hierarchy -check" for positional module args 2014-12-24 16:26:18 +01:00
Clifford Wolf bacd3699b3 Checking existence of ports in "hierarchy -check" 2014-12-19 18:47:19 +01:00