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726 Commits

Author SHA1 Message Date
Clifford Wolf a0dff87a57 Added "yosys -W regex" 2016-12-22 23:41:44 +01:00
Clifford Wolf f144adec58 Added AIGER back-end to automatic back-end detection 2016-12-21 10:16:47 +01:00
Clifford Wolf 00761de1b7 Bugfix in comment handling 2016-12-13 13:48:09 +01:00
Clifford Wolf a926a6afc2 Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
Clifford Wolf fa535c0b00 Some minor build fixes for Visual C 2016-10-14 18:36:02 +02:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf 59508c99b4 define PATH_MAX if not defined by limits.h 2016-10-11 12:12:09 +02:00
Clifford Wolf cb7dbf4070 Improvements in assertpmux 2016-09-07 12:42:16 +02:00
Clifford Wolf 6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 23afeadb5e Fixed handling of transparent bram rd ports on ROMs 2016-08-27 17:06:22 +02:00
Clifford Wolf f8a77abfac Added glob support to all front-ends 2016-08-22 15:05:57 +02:00
William D. Jones 5299b17056 Add MSYS2-compatible build. 2016-08-16 14:41:59 -04:00
Clifford Wolf 5767e4bc4d Use _Exit(0) on win32, always use _Exit(1) in log_error() 2016-08-16 09:38:54 +02:00
Clifford Wolf 39da8eddae Added log_const() API 2016-08-09 19:56:10 +02:00
Yury Gribov f7730d43bb Use /proc/self/exe on Cygwin as well. 2016-08-08 12:00:27 +02:00
Clifford Wolf 8d88fcb270 Added SatGen support for $anyconst 2016-07-27 15:52:20 +02:00
Clifford Wolf 9540be1d45 Removed $predict support from SatGen 2016-07-27 15:44:11 +02:00
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf a7b0769623 Added "read_verilog -dump_rtlil" 2016-07-27 15:40:17 +02:00
Clifford Wolf 8537c4d206 Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell() 2016-07-25 16:39:25 +02:00
Clifford Wolf b1c432af56 Improvements in CellEdgesDatabase 2016-07-24 17:21:53 +02:00
Clifford Wolf f162b858f2 Added CellEdgesDatabase API 2016-07-24 13:59:57 +02:00
Clifford Wolf 89deb412c6 Added satgen initstate support 2016-07-22 10:28:45 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Ruben Undheim a8200a773f A few modifications after pull request comments 
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
 2016-06-18 14:23:38 +02:00
Ruben Undheim 178ff3e7f6 Added support for SystemVerilog packages with localparam definitions 2016-06-18 10:53:55 +02:00
Clifford Wolf ebece2b8d5 Added $sop SAT model 2016-06-17 17:47:30 +02:00
Clifford Wolf 95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf 52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf 864eeadcd9 Added missing "#define HASHLIB_H" 2016-05-14 11:43:20 +02:00
Clifford Wolf 570014800a Include <cmath> in yosys.h 2016-05-08 10:50:39 +02:00
Clifford Wolf f103bfb9ba Fixes for MXE build 2016-05-07 10:53:18 +02:00
Clifford Wolf 9aa4b3309c Added "yosys -D ALL" 2016-04-24 17:12:34 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf a07f893a5f Minor hashlib bugfix 2016-04-16 23:20:11 +02:00
Clifford Wolf ace462237f Hashlib indenting fix 2016-04-05 13:25:23 +02:00
Clifford Wolf 2553319081 Added ScriptPass helper class for script-like passes 2016-03-31 11:16:34 +02:00
Clifford Wolf 6f1b6dc322 Added log_dump() support for dict<> and pool<> containers 2016-03-31 09:57:44 +02:00
Clifford Wolf 0db53284fd We have 2016 for a while now 2016-03-30 13:52:26 +02:00
Clifford Wolf 48dbc75bed Added .vhd file extension support 2016-03-30 13:24:49 +02:00
Clifford Wolf 95784437ac Merge pull request #137 from ravenexp/master 
Embed DATDIR make variable value into yosys binary.
 2016-03-28 16:54:23 +02:00
Sebastian Kuzminsky 73870c1edf fix a cut-n-paste error in the -h help 2016-03-26 11:15:35 -06:00
Sergey Kvachonok 963c0d2525 Embed DATDIR make variable value into yosys binary. 
Use it as the last resort in the share/ directory location search.
 2016-03-26 11:16:53 +03:00
Clifford Wolf 45af4a4acf Use easyer-to-read unoptimized ceil_log2() 
see here for details on the optimized version:
http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c
 2016-02-15 23:06:18 +01:00
Clifford Wolf 0c4b311242 Fixed more visual studio warnings 2016-02-14 09:35:25 +01:00
Clifford Wolf bcc873b805 Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
Clifford Wolf 0d7fd2585e Added "int ceil_log2(int)" function 2016-02-13 16:52:16 +01:00
Clifford Wolf ba407da187 Added addBufGate module method 2016-02-02 11:26:07 +01:00
Clifford Wolf 01bcc5663f SigMap performance improvement 2016-02-01 10:10:20 +01:00
Clifford Wolf ea492abcf0 hashlib mfp<> performance improvements 2016-02-01 10:03:03 +01:00
Clifford Wolf 13e15a24a2 Added reserve() method to haslib classes and 
calculate hashtable size based on entries capacity, not size
 2016-01-31 22:50:34 +01:00
Rick Altherr 3c48de8e21 rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*) 
Converting to a pool<SigBit> is fairly expensive due to inserts somewhat
frequently causing rehashing.  Instead, walk through the pattern SigSpec
directly on a chunk-by-chunk basis and apply it to this SigSpec's
individual bits.  Using chunks for the pattern minimizes the number of
iterations in the outer loop.
 2016-01-31 09:20:16 -08:00
Rick Altherr 0265d7b100 rtlil: speed up SigSpec::sort_and_unify() 
std::set<> internally is often a red-black tree which is fairly
expensive to create but fast to lookup.  In the case of
sort_and_unify(), a set<> is constructed as a temporary object to
attempt to speed up lookups.  Being a temporarily, however, the cost of
creation far outweights the lookup improvement and is a net performance
loss.  Instead, sort the vector<> that already exists and then apply
std::unique().
 2016-01-31 09:20:16 -08:00
Rick Altherr 89dc40f162 rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*) 2016-01-31 09:20:16 -08:00
Rick Altherr cd3e1095b0 rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*) 2016-01-31 09:20:16 -08:00
Clifford Wolf 5462399c88 Meaningless coding style change 2016-01-31 16:12:35 +01:00
Rick Altherr 43756559d8 rtlil: rewrite remove2() to avoid copying 2016-01-30 00:28:07 -08:00
Rick Altherr 12ebdef17c rtlil: duplicate remove2() for std::set<> 2016-01-29 23:06:40 -08:00
Rick Altherr 9e26147ccd rtlil: change IdString comparison operators to take references instead of copies 2016-01-29 23:06:40 -08:00
Clifford Wolf 33a5b28e25 Added default values for hashlib at() methods 2015-12-02 20:41:57 +01:00
Clifford Wolf 276101f032 Re-added SigMap::allbits() 2015-11-30 19:43:52 +01:00
Clifford Wolf 6459e3ac39 Removed dangling ';' in rtlil.h 2015-11-26 18:11:34 +01:00
Clifford Wolf 1e32e4bdae Improved SigMap performance 2015-10-28 11:21:55 +01:00
Clifford Wolf e69efec588 Improvements in new SigMap 2015-10-28 00:39:53 +01:00
Clifford Wolf f3db70d2f3 Removed old SigMap implementation 2015-10-27 15:09:44 +01:00
Clifford Wolf 09b4050f2e Added hashlib::mfp and new SigMap 2015-10-27 15:04:47 +01:00
Clifford Wolf d014ba2d0e Major refactoring of equiv_struct 2015-10-25 19:31:29 +01:00
Clifford Wolf 207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf da923c198e Added "equiv_add -cell" 2015-10-25 14:35:40 +01:00
Clifford Wolf 7f110e7018 renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() 2015-10-24 22:56:40 +02:00
Clifford Wolf a1c3df7fe4 Fixed driver conflict handling (various cmds) 2015-10-24 19:23:30 +02:00
Clifford Wolf 6fe48cf41e equiv_purge bugfix, using SigChunk in Yosys namespace 2015-10-24 19:09:45 +02:00
Clifford Wolf 2a0f577f83 Fixed handling of driver-driver conflicts in wreduce 2015-10-24 13:44:35 +02:00
Clifford Wolf 281a033e92 Added support for ":" as comment symbol after ;-parsing 2015-10-23 20:08:33 +02:00
Clifford Wolf 5d1c0ce7c0 Progress on cell help messages 2015-10-17 02:35:19 +02:00
Clifford Wolf 7d3a3a3173 Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf d212d4d0c1 Cosmetic fix in Module::addLut() 2015-09-18 21:55:12 +02:00
Andrei Errapart 522176c946 Removed unnecessary cast. 2015-09-01 12:40:36 +02:00
Andrei Errapart 09176bcf3f Microsoft Visual C++ fixes in hashlib; template specializations on int32_t and int64_t. 2015-09-01 12:40:24 +02:00
Andrei Errapart 744a5333f5 Microsoft Visual C++ fix for log.h. 2015-09-01 12:40:12 +02:00
Clifford Wolf ee8f6f31f4 Added SigMap::allbits() 2015-08-31 16:42:19 +02:00
Clifford Wolf ff50bc2ac3 Added $tribuf and $_TBUF_ cell types 2015-08-16 12:54:52 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf bc468cb6f2 Fixed hashlib for 64 bit int keys 2015-08-12 13:37:09 +02:00
Clifford Wolf 45ee2ba3b8 Fixed handling of [a-fxz?] in decimal constants 2015-08-11 11:32:37 +02:00
Clifford Wolf 8d6d5c30d9 Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf caa274ada6 Added design->rename(module, new_name) 2015-06-30 01:37:59 +02:00
Clifford Wolf 99100f367d Added "rename -top new_name" 2015-06-17 09:38:56 +02:00
Clifford Wolf ea23bb8aa4 Added "write_smv" skeleton 2015-06-15 00:46:27 +02:00
Clifford Wolf 4c733301e6 Fixed cstr_buf for std::string with small string optimization 2015-06-11 13:39:49 +02:00
Clifford Wolf 3a6abc9bf6 Improvements in cellaigs.cc and "json -aig" 2015-06-11 10:48:16 +02:00
Clifford Wolf 1ae360cf72 AigMaker refactoring 2015-06-10 23:00:12 +02:00
Clifford Wolf e534881794 Added "json -aig" 2015-06-10 08:13:56 +02:00