Eddie Hung
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f2d030a70f
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Be sensitive to signedness
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2019-09-10 15:14:55 -07:00 |
Eddie Hung
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76eedee089
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Really get rid of 'opt_expr -fine' by being explicit
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2019-09-10 14:26:12 -07:00 |
Eddie Hung
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e35dfc5ab5
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Only swap ports if $mul and not $__mul
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2019-08-13 16:52:15 -07:00 |
Eddie Hung
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2a1b98d478
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Add DSP_A_MAXWIDTH_PARTIAL, refactor
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2019-08-13 10:21:24 -07:00 |
Eddie Hung
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105aaeaf59
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Trim Y_WIDTH
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2019-08-01 14:33:16 -07:00 |
Eddie Hung
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65de9aaaa9
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Add DSP_SIGNEDONLY back
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2019-08-01 14:29:00 -07:00 |
Eddie Hung
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915f4e34bf
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DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
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2019-08-01 13:20:34 -07:00 |
Eddie Hung
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332b86491d
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Revert "Do not do sign extension in techmap; let packer do it"
This reverts commit 595a8f032f .
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2019-08-01 12:17:14 -07:00 |
Eddie Hung
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7e86c8bcfb
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Fix B_WIDTH > DSP_B_MAXWIDTH case
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2019-08-01 10:01:43 -07:00 |
Eddie Hung
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d2c33863d0
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Do not compute sign bit if result is zero
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2019-07-31 16:04:19 -07:00 |
Eddie Hung
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60c4887d15
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For signed multipliers, compute sign bit separately...
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2019-07-31 15:45:41 -07:00 |
Eddie Hung
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2f71c2c219
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Fix spacing
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2019-07-26 15:30:51 -07:00 |
Eddie Hung
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c39ccc65e9
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Add copyright header, comment on cascade
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2019-07-24 10:49:09 -07:00 |
Eddie Hung
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151c5c96c0
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Typo for Y_WIDTH
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2019-07-23 15:05:20 -07:00 |
Eddie Hung
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3a7aeb028d
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Use minimum sized width wires
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2019-07-22 13:01:26 -07:00 |
Eddie Hung
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47fd042b9f
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Indirection via $__soft_mul
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2019-07-19 20:20:33 -07:00 |
Eddie Hung
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595a8f032f
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Do not do sign extension in techmap; let packer do it
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2019-07-19 15:50:13 -07:00 |
Eddie Hung
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bba72f03dd
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Do not $mul -> $__mul if A and B are less than maxwidth
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2019-07-19 11:54:26 -07:00 |
Eddie Hung
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1d14cec7fd
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Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too
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2019-07-19 11:39:24 -07:00 |
Eddie Hung
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7bdb3996e2
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Merge branch 'xc7dsp' into ice40dsp
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2019-07-19 10:28:38 -07:00 |
Eddie Hung
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ca94c2d3c4
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Fix typo in B
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2019-07-19 10:27:44 -07:00 |
Eddie Hung
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2168568f43
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Use sign_headroom instead
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2019-07-19 09:16:13 -07:00 |
Eddie Hung
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15c2a79ab9
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Do not define `DSP_SIGNEDONLY macro if no exists
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2019-07-18 16:04:58 -07:00 |
Eddie Hung
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2339b7fc37
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mul2dsp to create cells that can be interchanged with $mul
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2019-07-18 15:37:35 -07:00 |
Eddie Hung
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e22a752242
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Make consistent
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2019-07-18 15:21:23 -07:00 |
Eddie Hung
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8326af5418
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Fix signed multiplier decomposition
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2019-07-18 13:11:26 -07:00 |
Eddie Hung
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2024357f32
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Working for unsigned
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2019-07-18 10:53:18 -07:00 |
Eddie Hung
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d5cd2c80be
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Cleanup
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2019-07-18 09:20:48 -07:00 |
David Shah
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16b0ccf04c
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mul2dsp: Lower partial products always have unsigned inputs
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-18 11:33:37 +01:00 |
Eddie Hung
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8dca8d486e
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Fix mul2dsp signedness
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2019-07-17 12:44:52 -07:00 |
Eddie Hung
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1b62b82e05
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A_SIGNED == B_SIGNED so flip both
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2019-07-17 11:34:18 -07:00 |
Eddie Hung
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0b6d47f8bf
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Add DSP_{A,B}_SIGNEDONLY macro
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2019-07-16 15:55:13 -07:00 |
Eddie Hung
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569cd66764
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Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
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2019-07-16 14:18:36 -07:00 |
David Shah
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8da4c1ad82
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mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-16 16:44:40 +01:00 |
David Shah
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7a75f5f3ac
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mul2dsp: Fix indentation
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-16 16:19:32 +01:00 |
Eddie Hung
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fd5b3593d8
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Do not swap if equals
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2019-07-15 16:52:37 -07:00 |
Eddie Hung
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42f8e68e76
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OUT port to Y in generic DSP
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2019-07-15 14:45:47 -07:00 |
Eddie Hung
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91fcf034bc
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Only swap if B_WIDTH > A_WIDTH
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2019-07-15 11:24:11 -07:00 |
Eddie Hung
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1793e6018a
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Tidy up
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2019-07-15 11:19:54 -07:00 |
David Shah
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e78864993a
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mul2dsp: Fix typo
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-08 18:42:41 +01:00 |
David Shah
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269ff450f5
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Add mul2dsp multiplier splitting rule and ECP5 mapping
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-08 18:42:09 +01:00 |