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7874 Commits

Author SHA1 Message Date
Eddie Hung 0adf81cb91 Add $alu tests 2019-08-09 12:13:17 -07:00
Eddie Hung 9f1b82f594 opt_expr -fine to trim LSBs of $alu too 2019-08-09 10:32:12 -07:00
Eddie Hung 8350dfb809 Add alumacc versions of opt_expr tests 2019-08-09 10:30:53 -07:00
Eddie Hung 9300111601 Add new $alu test, remove wreduce 2019-08-09 10:22:06 -07:00
Clifford Wolf 6d0be8d206 Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes #1273 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-09 19:17:59 +02:00
Eddie Hung 313c9ec8df Cleanup some more 2019-08-09 10:13:49 -07:00
whitequark 39f4c1096a
Merge pull request #1267 from whitequark/proc_prune-fix-1243 
proc_prune: fix handling of exactly identical assigns
 2019-08-09 17:10:46 +00:00
Eddie Hung d9c1664462 Simplify opt_expr tests using equiv_opt 2019-08-09 10:08:17 -07:00
Eddie Hung acfb672d34 A bit more on where $lcu comes from 2019-08-09 09:50:47 -07:00
Eddie Hung 5aef998957 Add more comments 2019-08-09 09:48:17 -07:00
Eddie Hung 446dcb3ed3 Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro 2019-08-09 09:17:35 -07:00
Miodrag Milanovic d51b135e33 Fix CO 2019-08-09 12:37:10 +02:00
Miodrag Milanovic 7a860c5623 Merge remote-tracking branch 'upstream/master' into efinix 2019-08-09 09:46:37 +02:00
Miodrag Milanovic 8853d6d232 ABC requires it like this 2019-08-09 08:54:17 +02:00
Miodrag Milanovic 5130a65865 Propagate parameters for Travis build 2019-08-09 08:06:14 +02:00
Eddie Hung 747690a6df Remove muxY and ffY for now 2019-08-08 16:33:37 -07:00
Eddie Hung 1f722b3500 Remove signed from ports in +/xilinx/dsp_map.v 2019-08-08 16:33:20 -07:00
Eddie Hung 2c0be7aa5d Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing 2019-08-08 12:56:05 -07:00
Eddie Hung 162eab6b74 Combine techmap calls 2019-08-08 10:55:48 -07:00
Eddie Hung 07e50b9c25 Only pack registers if {A,B,P}REG = 0, do not pack $dffe 2019-08-08 10:51:19 -07:00
Eddie Hung 7160243874 Move xilinx_dsp to before alumacc 2019-08-08 10:45:56 -07:00
Eddie Hung 911129e3ef Disable $dffe 2019-08-08 10:44:49 -07:00
Eddie Hung 57b2e4b9c1 INMODE is 5 bits 2019-08-08 10:44:35 -07:00
Eddie Hung 13cc106cf7 Fix copy-pasta typo 2019-08-08 10:44:26 -07:00
Eddie Hung dae7c59358 Add a few comments to document $alu and $lcu 2019-08-08 10:05:28 -07:00
Eddie Hung ac2fc3a144
Merge pull request #1264 from YosysHQ/eddie/fix_1254 
opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
 2019-08-08 07:58:33 -07:00
Eddie Hung 61d7f1997b
Merge pull request #1266 from YosysHQ/eddie/ice40_full_adder 
Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER
 2019-08-08 07:58:11 -07:00
David Shah 0492b8b541 ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 15:18:59 +01:00
David Shah cb84ed2326 ecp5: Bring up to date with mul2dsp changes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 15:14:09 +01:00
David Shah 83b2e02723 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-08 11:40:09 +01:00
David Shah b8cd4ad64a DSP48E1 sim model: add SIMD tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:39:35 +01:00
David Shah 57aeb4cc01 DSP48E1 model: test CE inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:32:43 +01:00
David Shah d60b3c0dc8 DSP48E1 sim model: fix seq tests and add preadder tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:18:37 +01:00
David Shah e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:52:04 +01:00
David Shah f6605c7dc0 DSP48E1 sim model: Comb, no pre-adder, mode working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:26:44 +01:00
David Shah f0f352e971 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:05:11 +01:00
David Shah ccfb4ff2a9 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 09:31:34 +01:00
whitequark 0b09a347dc proc_prune: fix handling of exactly identical assigns. 
Before this commit, in a process like:
   process $proc$bug.v:8$3
     assign $foo \bar
     switch \sel
       case 1'1
         assign $foo 1'1
         assign $foo 1'1
       case
         assign $foo 1'0
     end
   end
both of the "assign $foo 1'1" would incorrectly be removed.

Fixes #1243.
 2019-08-08 05:32:35 +00:00
Eddie Hung 8bf45f34c4 Remove dump call 2019-08-07 21:36:02 -07:00
Eddie Hung 2b6cdfb39f Move tests/various/opt* into tests/opt/ 2019-08-07 21:35:48 -07:00
Eddie Hung d5e8c0e6d3 Remove ice40_unlut call, simply do equiv_opt on synth_ice40 2019-08-07 21:33:56 -07:00
Eddie Hung 35bf509603 Add testcase from removed opt_ff.{v,ys} 2019-08-07 21:31:32 -07:00
Eddie Hung 4545bf482f Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run 2019-08-07 16:48:38 -07:00
Eddie Hung 9776084eda Allow whitebox modules to be overwritten 2019-08-07 16:40:24 -07:00
Eddie Hung 9962e6fc1a Update CHANGELOG 2019-08-07 16:33:46 -07:00
Eddie Hung 675c1d4218 Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER 2019-08-07 16:29:38 -07:00
Eddie Hung cc331cf70d Add test 2019-08-07 16:29:38 -07:00
Eddie Hung ea8ac8fd74 Remove ice40_unlut 2019-08-07 16:29:38 -07:00
Eddie Hung 6b314c8371 Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER 2019-08-07 16:29:38 -07:00
Eddie Hung fb568ddb4e Fix compile error 2019-08-07 14:31:55 -07:00