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2431 Commits

Author SHA1 Message Date
Krystine Sherwin 600149a824
Docs: Add back message for empty help 2024-10-15 07:16:39 +13:00
Krystine Sherwin 6bbe763845
Docs: Put cell library help strings into a struct 
Allows for more expressive code when constructing help messages for cells.
Will also move extra logic in parsing help strings into the initial python parse instead of doing it in the C++ at export time.
 2024-10-15 07:16:39 +13:00
Emil J 1113b88cb2
Merge pull request #4649 from YosysHQ/emil/synth-xilinx-json 
synth_xilinx: add -json
 2024-10-14 06:45:14 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Emil J. Tywoniak 981b267d97 synth_xilinx: add -json 2024-10-09 19:24:32 +02:00
Martin Povišer 9018d06a33 quicklogic: Avoid carry chains in division mapping 
The default mapping rules for division-like operations (div/divfloor/
mod/modfloor) invoke subtractions which can get mapped to carry chains
in FPGA flows. Optimizations across carry chains are weak, so in
practice this ends up too costly compared to implementing the division
purely in soft logic.

For this reason arrange for `techmap.v` ignoring division operations
under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry
chains for divisions.
 2024-09-19 12:18:47 +02:00
Martin Povišer eeffca9470 simlib: Add `$buf` disclaimer 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 4d469f461b Add coarse-grain $buf buffer cell type 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
YRabbit ab35dff702 Gowin. Add the EMCU primitive. 
EMCU is a micro-processor based on ARM Cortex-M3 embedded in the
GW1NSR-4C chip used in the Tangnano4k board.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-09-11 10:18:51 +10:00
Miodrag Milanović 598d010349
Merge pull request #4504 from YosysHQ/nanoxplore 
NanoXplore synthesis
 2024-09-03 10:19:44 +02:00
Miodrag Milanovic 556c705a89 Cleanup of synth_nanoxplore pass 2024-09-03 10:15:50 +02:00
Emil J d901b28d2c
Merge pull request #4546 from NachtSpyder04/main 
[Docs]:Add new cell type help messages
 2024-08-19 15:50:41 +02:00
David Lanzendörfer d1b767ea8b Adding missing to Gowin tech files 
Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip
design for my Sipeed Tang FPGA fails.
 2024-08-18 19:38:31 +01:00
NachtSpyder04 aa60255e0e update help messages that went beyond line length limit 2024-08-18 20:27:35 +05:30
Saish Karole 34aabd56cc
Apply suggestions from code review 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-08-18 20:12:53 +05:30
Saish Karole d80d4dc51c
[Docs]:Add new cell type help messages (#1) 
* add shift operators description

* update shift operations' descriptions, add desciptions for add, sub, logic_*, tribuf, mux, demux, concat, pow and comparison operators
 2024-08-17 15:47:00 +05:30
Miodrag Milanovic 54d237ff82 add min_ce_use and min_srst_use parameters 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 14e43139cb Run opt_merge, helps with inverted reset/load signals 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 220ddeac4d Set -mince and -minsrst 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dbf1d037e8 Cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7bf623a0c7 Fix simulation model warnings 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 262ad03cd3 Add iopads by default add option to disable and keep old one for compatibility 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8f806c0d12 Added DDFR support 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 1a6e5c671f Add meminit handling for NX_RFB_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 6876a27547 Add NX_DFR simulation model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic eb30be6189 Impulse does not support these types but NG-ULTRA architecture does 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7601dc740b Some memory types are only supported on NG-LARGE 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4372487a6f raw must be 16 bits for nx tools to work 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f8ae93c0ea run setundef for all x inputs 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 40f05009e3 Fix CY chaining and CI injection 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 596506b88b Add NX_XCDC_U to wrappers 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8909a42796 Better wire check 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 5766555642 Support brams with initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4aaab8f395 start adding wfg model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41a86fdb2c fix 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f4d8ea4c40 Start adding RFB simulation models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8eb099c1f4 remove debug attribute 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 829dd62054 block ram mapping for standard modes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 9d6b47466f Add RF initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7e4aef06e4 Add register file mapping 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 11449ec493 Cleanup not connected ports 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f9f68c3cd1 Split sim models into multiple files and implement few 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 04d3672121 No need for LOC 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41ae513d60 support other I/O configurations 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 645888cff5 cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 9a9190b67d enable dff context initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dc16bdd85b DFF reset and context must be in sync 2024-08-15 17:50:36 +02:00
Miodrag Milanovic cb45f8b69d Fixed of mapping and initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 198fc963ca Add new DFF types, and added "-nodffe" option 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 0c4bbf7e4b Fix existing DFF mapping and add new types 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 94675a5e0b Fix dff simulation model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 606439b44c do not leave NX_RAM empty to prevent removing it 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4cb8e62626 Properly map ff ram 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 1591d258a9 Made NX_CY model more robust 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dac4f04460 add latch mapping, and remove aldff for now 2024-08-15 17:50:36 +02:00
Miodrag Milanovic cf21b48bfd fix co on nx_cy 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 31f943513b set add_carry property and all inputs to 0 2024-08-15 17:50:36 +02:00
Miodrag Milanovic b6f7383736 break long chains 2024-08-15 17:50:36 +02:00
Miodrag Milanovic ab32dde81b optimized 2024-08-15 17:50:36 +02:00
Miodrag Milanovic da6a62f3a0 Initial carry chain handling pass 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 474ed28aee added no-rw-check, and new rfb models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic a5bfb23b47 start cleaning rams 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 370517b1e6 IO 2024-08-15 17:50:36 +02:00
Miodrag Milanovic fa14c600ff commented remainder of primitives 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8023f921e3 RAM 2024-08-15 17:50:36 +02:00
Miodrag Milanovic b202126c76 IOM 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 71f0984dc9 fixes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic ef15325dce removed virtual primitive 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f836de6bcc mark DSPs as TODOs for now 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8f42d6dace fifo 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 012f0e2952 memory blocks 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 3ed5ea24b2 sortout more blackboxes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 0ecc2e597f PLLs 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 200e1a7bfe more DSP wrappers 2024-08-15 17:50:36 +02:00
Miodrag Milanovic ce635abc21 NX_DSP/SPLIT 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 60611b936b CDC_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 815622f685 CDC_L wrappers 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 827ea11503 start splitting blackboxes and add wrapper techmap 2024-08-15 17:50:36 +02:00
Miodrag Milanovic cfce7dd2f8 remove soc 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 9700971a8a just copy LOC 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 989eef29b2 produce less cells 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 74289b7339 remove init from sdff 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4c1f84a686 add io mapping 2024-08-15 17:50:36 +02:00
Lofty b0c4add642 Added lutram 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 5d898ab223 Add blackboxes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8374f0336d add family and ability to disable carry chains 2024-08-15 17:50:36 +02:00
Lofty b3f59c9820 Add NX_CY 2024-08-15 17:50:36 +02:00
Lofty b4e9bb0d85 Add FFs and related tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 94b6f19cf0 Make lut init match vendor tools 2024-08-15 17:50:36 +02:00
Lofty 3b48e9df61 Add initial NanoXplore pass 2024-08-15 17:50:36 +02:00
N. Engelhardt 9f869b265c
Merge pull request #4474 from tony-min-1/mchp 
Add PolarFire FPGA support
 2024-07-29 15:28:44 +02:00
Emil J 43c1328fbb
Merge pull request #4479 from yrabbit/z1-power 
Gowin. Add an energy saving primitive
 2024-07-18 11:56:00 +02:00
YRabbit 19bbdd8800 Gowin. Add the DCS primitive 
Not so much adding the primitive itself, but only its DCS_MODE
parameter, without which an error occurs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-07-11 21:39:44 +10:00
chunlin min 3db69b7a10 inline all tests. Add switch to remove init values as PolarFire DFFs do not support init 2024-07-08 17:03:03 -04:00
chunlin min 0afb5e28fb cosmetic changes 2024-07-08 15:10:44 -04:00
chunlin min af67c745c4 initialize argidx to 1 2024-07-08 11:41:41 -04:00
chunlin min a0c9d10118 undo last change, to investigate dff_opt test failure 2024-07-08 11:30:52 -04:00
chunlin min 3c95a28dc2 fix compile warning 2024-07-08 11:13:53 -04:00
Tony Min d41688f7d7
Revisions (#4) 
* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
 2024-07-08 10:57:16 -04:00
YRabbit 9d0bca9775 Gowin. Add an energy saving primitive 
We add a BANDGAP primitive used to turn off power to OSC, PLL and other
things on some GOWIN chips.

We also mark this primitive and GSR as keep.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-07-06 18:58:21 +10:00