mirror of https://github.com/YosysHQ/yosys.git
Initial carry chain handling pass
This commit is contained in:
Miodrag Milanovic
parent
474ed28aee
commit
da6a62f3a0
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@ -1,5 +1,6 @@
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OBJS += techlibs/nanoxplore/synth_nanoxplore.o
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OBJS += techlibs/nanoxplore/nx_carry.o
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# Techmap
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
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@ -1,4 +1,21 @@
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`default_nettype none
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2024 Miodrag Milanovic <micko@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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(* techmap_celltype = "$alu" *)
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module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
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@ -26,46 +43,32 @@ module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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function integer round_up4;
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input integer N;
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begin
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round_up4 = ((N + 3) / 4) * 4;
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end
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endfunction
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localparam Y_WIDTH4 = round_up4(Y_WIDTH);
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(* force_downto *)
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wire [Y_WIDTH4-1:0] AA = A_buf;
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH4-1:0] BB = BI ? ~B_buf : B_buf;
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(* force_downto *)
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wire [Y_WIDTH4-1:0] BX = B_buf;
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(* force_downto *)
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wire [Y_WIDTH4:0] C = {CO, CI};
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(* force_downto *)
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wire [Y_WIDTH4-1:0] FCO, Y1;
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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genvar i;
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generate for (i = 0; i < Y_WIDTH4; i = i + 4) begin:slice
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NX_CY cy_i (
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.CI(C[i]),
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.A1(AA[i]), .A2(AA[i+1]), .A3(AA[i+2]), .A4(AA[i+3]),
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.B1(BB[i]), .B2(BB[i+1]), .B3(BB[i+2]), .B4(BB[i+3]),
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.S1(Y1[i]), .S2(Y1[i+1]), .S3(Y1[i+2]), .S4(Y1[i+3]),
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.CO(FCO[i])
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);
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
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NX_CY_1BIT #(.first(i==0))
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alu_i (
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.CI(i==0 ? CI : CO[i-1]),
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.A(AA[i]),
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.B(BB[i]),
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.S(Y[i]),
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.CO(CO[i])
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);
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assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
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if (i+1 < Y_WIDTH)
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assign CO[i+1] = (AA[i+1] && BB[i+1]) || (C[i+1] && (AA[i+1] || BB[i+1]));
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if (i+2 < Y_WIDTH)
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assign CO[i+2] = (AA[i+2] && BB[i+2]) || (C[i+2] && (AA[i+2] || BB[i+2]));
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if (i+3 < Y_WIDTH)
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assign CO[i+3] = FCO[i];
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end: slice
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endgenerate
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end endgenerate
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NX_CY_1BIT alu_cout(
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.CI(CO[Y_WIDTH-1]),
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.A(1'b0),
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.B(1'b0),
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.S(CO[Y_WIDTH-1])
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);
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assign X = AA ^ BB;
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assign Y = Y1[Y_WIDTH-1:0];
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/* End implementation */
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assign X = AA ^ BB;
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endmodule
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@ -184,4 +184,16 @@ module NX_IOB_O(I, C, T, IO);
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assign IO = C ? I : 1'bz;
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endmodule
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(* abc9_box, lib_whitebox *)
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module NX_CY_1BIT(CI, A, B, S, CO);
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(* abc9_carry *)
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input CI;
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input A;
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input B;
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output S;
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(* abc9_carry *)
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output CO;
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parameter first = 1'b0;
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assign {CO, S} = A + B + CI;
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endmodule
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@ -0,0 +1,158 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2024 Miodrag Milanovic <micko@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static SigBit get_bit_or_zero(const SigSpec &sig)
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{
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if (GetSize(sig) == 0)
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return State::S0;
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return sig[0];
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}
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static void nx_carry_chain(Module *module)
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{
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SigMap sigmap(module);
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dict<Cell*,SigBit> carry_ci_propagate;
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for (auto cell : module->cells())
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{
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if (cell->type == ID(NX_CY_1BIT)) {
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// Only first can have CI generated that is not constant
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if (cell->getParam(ID(first)).as_int() == 0) continue;
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if (!cell->getPort(ID(CI)).is_wire()) continue;
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carry_ci_propagate[cell] = cell->getPort(ID(CI)).as_bit();
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}
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}
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for (auto cy : carry_ci_propagate)
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{
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Cell *cell = cy.first;
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cell->setParam(ID(first), Const(0, 1));
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SigBit new_co = module->addWire(NEW_ID);
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Cell *c = module->addCell(NEW_ID, ID(NX_CY_1BIT));
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c->setParam(ID(first), Const(1));
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c->setPort(ID(CI), State::S0);
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c->setPort(ID(A), cy.second);
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c->setPort(ID(B), State::S0);
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c->setPort(ID(CO), new_co);
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cell->setPort(ID(CI), new_co);
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log("Adding cell %s to propaget CI signal.\n", log_id(cell));
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}
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carry_ci_propagate.clear();
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dict<SigBit,Cell*> carry;
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for (auto cell : module->cells())
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{
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if (cell->type == ID(NX_CY_1BIT)) {
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if (cell->getParam(ID(first)).as_int() == 1) continue;
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if (!cell->hasPort(ID(CI)))
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log_error("Not able to find connected carry.\n");
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SigBit ci = sigmap(cell->getPort(ID(CI)).as_bit());
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carry[ci] = cell;
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}
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}
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dict<Cell*,vector<Cell*>> carry_chains;
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log("Detecting carry chains\n");
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for (auto cell : module->cells())
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{
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if (cell->type == ID(NX_CY_1BIT)) {
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if (cell->getParam(ID(first)).as_int() == 0) continue;
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vector<Cell*> chain;
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SigBit co = sigmap(cell->getPort(ID(CO)).as_bit());
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Cell *current = cell;
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chain.push_back(current);
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while (co.is_wire())
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{
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if (carry.count(co)==0)
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break;
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//log_error("Not able to find connected carry.\n");
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current = carry[co];
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chain.push_back(current);
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if (!current->hasPort(ID(CO))) break;
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co = sigmap(current->getPort(ID(CO)).as_bit());
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}
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carry_chains[cell] = chain;
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}
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}
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log("Creating NX_CY cells.\n");
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for(auto& c : carry_chains) {
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Cell *cell = nullptr;
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int j = 0;
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IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) };
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IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) };
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IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
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for (size_t i=0 ; i<c.second.size(); i++) {
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if (j==0) {
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cell = module->addCell(NEW_ID, ID(NX_CY));
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cell->setPort(ID(CI), c.second.at(i)->getPort(ID(CI)));
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}
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if (j==3)
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cell->setPort(ID(CO), c.second.at(i)->getPort(ID(CO)));
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cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A))));
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cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B))));
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if (c.second.at(i)->hasPort(ID(S)))
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cell->setPort(names_S[j], c.second.at(i)->getPort(ID(S)));
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j = (j + 1) % 4;
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module->remove(c.second.at(i));
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}
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}
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}
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struct NXCarryPass : public Pass {
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NXCarryPass() : Pass("nx_carry", "NanoXplore: create carry cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" nx_carry [options] [selection]\n");
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log("\n");
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log("Fixes carry chain if needed, break it on 24 elements and group by 4 into NX_CY.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing NX_CARRY pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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nx_carry_chain(module);
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}
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} NXCarryPass;
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PRIVATE_NAMESPACE_END
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@ -279,8 +279,10 @@ struct SynthNanoXplorePass : public ScriptPass
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{
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if (nocy)
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run("techmap");
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else
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else {
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run("techmap -map +/techmap.v -map +/nanoxplore/arith_map.v");
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run("nx_carry");
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}
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if (help_mode || iopad) {
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run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -inpad $__BEYOND_IBUF O:PAD A:top", "(only if '-iopad')");
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run("techmap -map +/nanoxplore/io_map.v");
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