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Add NX_CY

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Lofty 2024-03-01 11:10:52 +01:00 committed by Miodrag Milanovic
parent b4e9bb0d85
commit b3f59c9820
4 changed files with 88 additions and 0 deletions
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1
techlibs/nanoxplore/Makefile.inc
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@ -2,5 +2,6 @@
OBJS += techlibs/nanoxplore/synth_nanoxplore.o
# Techmap
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))

71
techlibs/nanoxplore/arith_map.v Normal file
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@ -0,0 +1,71 @@
`default_nettype none
(* techmap_celltype = "$alu" *)
module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
function integer round_up4;
input integer N;
begin
round_up4 = ((N + 3) / 4) * 4;
end
endfunction
localparam Y_WIDTH4 = round_up4(Y_WIDTH);
(* force_downto *)
wire [Y_WIDTH4-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH4-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH4-1:0] BX = B_buf;
(* force_downto *)
wire [Y_WIDTH4:0] C = {CO, CI};
(* force_downto *)
wire [Y_WIDTH4-1:0] FCO, Y1;
genvar i;
generate for (i = 0; i < Y_WIDTH4; i = i + 4) begin:slice
NX_CY cy_i (
.CI(C[i]),
.A1(AA[i]), .A2(AA[i+1]), .A3(AA[i+2]), .A4(AA[i+3]),
.B1(BB[i]), .B2(BB[i+1]), .B3(BB[i+2]), .B4(BB[i+3]),
.S1(Y1[i]), .S2(Y1[i+1]), .S3(Y1[i+2]), .S4(Y1[i+3]),
.CO(FCO[i])
);
assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
if (i+1 < Y_WIDTH)
assign CO[i+1] = (AA[i+1] && BB[i+1]) || (C[i+1] && (AA[i+1] || BB[i+1]));
if (i+2 < Y_WIDTH)
assign CO[i+2] = (AA[i+2] && BB[i+2]) || (C[i+2] && (AA[i+2] || BB[i+2]));
if (i+3 < Y_WIDTH)
assign CO[i+3] = FCO[i];
end endgenerate
assign X = AA ^ BB;
assign Y = Y1[Y_WIDTH-1:0];
endmodule

6
techlibs/nanoxplore/cells_sim.v
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@ -33,3 +33,9 @@ always @(posedge clock, posedge async_reset)
else O <= I;
endmodule
module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);
parameter add_carry = 0;
assign {CO, S4, S3, S2, S1} = {A4, A3, A2, A1} + {B4, B3, B2, B1} + CI;
endmodule

10
tests/arch/nanoxplore/add_sub.ys Normal file
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@ -0,0 +1,10 @@
read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 2 t:NX_CY
select -assert-count 4 t:NX_LUT
select -assert-none t:NX_CY t:NX_LUT %% t:* %D