mirror of https://github.com/YosysHQ/yosys.git
42 lines
1.0 KiB
Verilog
42 lines
1.0 KiB
Verilog
module NX_LUT(input I1, I2, I3, I4, output O);
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parameter lut_table = 16'h0000;
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wire [7:0] s1 = I4 ? lut_table[15:8] : lut_table[7:0];
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wire [3:0] s2 = I3 ? s1[7:4] : s1[3:0];
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wire [1:0] s3 = I2 ? s2[3:2] : s2[1:0];
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assign O = I1 ? s3[1] : s3[0];
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endmodule
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module NX_DFF(input I, CK, L, R, output reg O);
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parameter dff_ctxt = 1'bx;
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parameter dff_edge = 1'b0;
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parameter dff_init = 1'b0;
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parameter dff_load = 1'b0;
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parameter dff_sync = 1'b0;
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parameter dff_type = 1'b0;
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initial begin
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O = dff_ctxt;
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end
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wire clock = CK ^ dff_edge;
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wire load = (dff_type == 2) ? (dff_load ? L : 1'bx) : dff_type;
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wire async_reset = !dff_sync && dff_init && R;
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wire sync_reset = dff_sync && dff_init && R;
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always @(posedge clock, posedge async_reset)
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if (async_reset) O <= load;
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else if (sync_reset) O <= load;
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else O <= I;
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endmodule
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module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);
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parameter add_carry = 0;
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assign {CO, S4, S3, S2, S1} = {A4, A3, A2, A1} + {B4, B3, B2, B1} + CI;
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endmodule
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