mirror of https://github.com/YosysHQ/yosys.git
add latch mapping, and remove aldff for now
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cf21b48bfd
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dac4f04460
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@ -17,6 +17,7 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/latches_map.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_l.txt))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_m.txt))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt))
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@ -43,13 +43,13 @@ module dff(input D, C, R, output Q);
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
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endmodule
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(* techmap_celltype = "$_ALDFF_[NP]P_" *)
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module aldff(input D, C, L, AD, output Q);
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parameter _TECHMAP_CELLTYPE = "$_ALDFF_PP_";
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localparam dff_edge = _TECHMAP_CELLTYPE[8*8 +: 8] == "N";
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(2)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(AD), .R(L), .O(Q));
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endmodule
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//(* techmap_celltype = "$_ALDFF_[NP]P_" *)
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//module aldff(input D, C, L, AD, output Q);
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// parameter _TECHMAP_CELLTYPE = "$_ALDFF_PP_";
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// localparam dff_edge = _TECHMAP_CELLTYPE[8*8 +: 8] == "N";
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// wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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// NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(2)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(AD), .R(L), .O(Q));
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//endmodule
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module \$_SDFF_PP0_ (input D, C, R, output Q);
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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@ -0,0 +1,11 @@
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module \$_DLATCH_N_ (E, D, Q);
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wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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input E, D;
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output Q = !E ? D : Q;
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endmodule
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module \$_DLATCH_P_ (E, D, Q);
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wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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input E, D;
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output Q = E ? D : Q;
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endmodule
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@ -294,7 +294,8 @@ struct SynthNanoXplorePass : public ScriptPass
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if (check_label("map_ffs"))
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{
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run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_ALDFF_?P_ 0 -cell $_SDFF_?P?_ 0");
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run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_SDFF_?P?_ 0 -cell $_DLATCH_?_ x"); //-cell $_ALDFF_?P_ 0
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run("techmap -map +/nanoxplore/latches_map.v");
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run("techmap -map +/nanoxplore/cells_map.v");
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run("opt_expr -undriven -mux_undef");
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run("clean -purge");
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