riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

fix co on nx_cy

This commit is contained in:
Miodrag Milanovic 2024-04-07 19:38:47 +02:00
parent 31f943513b
commit cf21b48bfd
1 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
techlibs/nanoxplore/arith_map.v
View File

@ -35,6 +35,8 @@ module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
@ -52,18 +54,18 @@ module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
NX_CY_1BIT #(.first(i==0))
alu_i (
.CI(i==0 ? CI : CO[i-1]),
.CI(i==0 ? CI : COx[i-1]),
.A(AA[i]),
.B(BB[i]),
.S(Y[i]),
.CO(CO[i])
.CO(COx[i])
);
end: slice
endgenerate
NX_CY_1BIT alu_cout(
.CI(CO[Y_WIDTH-1]),
.CI(COx[Y_WIDTH-1]),
.A(1'b0),
.B(1'b0),
.S(CO[Y_WIDTH-1])