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Fix dff simulation model

This commit is contained in:
Miodrag Milanovic 2024-04-29 08:06:01 +02:00
parent 606439b44c
commit 94675a5e0b
1 changed files with 4 additions and 4 deletions
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8
techlibs/nanoxplore/cells_sim.v
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@ -25,14 +25,14 @@ initial begin
end
wire clock = CK ^ dff_edge;
wire load = (dff_type == 2) ? (dff_load ? L : 1'bx) : dff_type;
wire load = dff_load ? L : 1'b1;
wire async_reset = !dff_sync && dff_init && R;
wire sync_reset = dff_sync && dff_init && R;
always @(posedge clock, posedge async_reset)
if (async_reset) O <= load;
else if (sync_reset) O <= load;
else O <= I;
if (async_reset) O <= dff_type;
else if (sync_reset) O <= dff_type;
else if (load) O <= I;
endmodule