2431 Commits

Author	SHA1	Message	Date
Emil J. Tywoniak	caf921161c	quicklogic: ql_dsp_io_regs debug print	2025-03-06 18:01:28 +01:00
Emil J. Tywoniak	1def0bc951	quicklogic: ql_dsp_macc set fractured mode	2025-03-06 18:00:23 +01:00
Emil J. Tywoniak	ebbac1f421	quicklogic: allow fractured mode on canonical dspv1 modules	2025-03-06 12:55:26 +01:00
Emil J. Tywoniak	6685f92c93	quicklogic: ql_dsp_simd remove unused MODE_BITS packing	2025-03-06 12:54:36 +01:00
Emil J. Tywoniak	7514c4738a	quicklogic: update dspv2_sim.v to v1.1 Feb21	2025-03-06 11:25:01 +01:00
Emil J. Tywoniak	a8c10eea03	quicklogic: ql_dsp_simd add dspv2 support, fix dspv1	2025-03-06 11:25:01 +01:00
Emil J. Tywoniak	434334ba63	ql_dsp_macc: whitespace. NFC	2025-02-27 17:41:57 +01:00
Emil J. Tywoniak	c1d2107fe0	ql_dsp_macc: dspv2	2025-02-27 17:41:57 +01:00
Emil J. Tywoniak	30473c4899	synth_quicklogic: enable dspv2 tests, fix -dspv2	2025-02-27 17:41:57 +01:00
Emil J. Tywoniak	402ca82503	synth_quicklogic: add -dspv2 to opt into v2 DSP blocks	2025-02-27 17:41:57 +01:00
Martin Povišer	9035abdcd6	qlf_k6n10f: Fix DSPV2 models	2025-02-20 11:30:24 +01:00
Martin Povišer	d600245ccf	qlf_k6n10f: New ql_dsp pass, move to DSPV2	2025-02-20 11:30:17 +01:00
Emil J. Tywoniak	a58481e9b7	mark all hash_into methods nodiscard	2025-01-14 12:39:15 +01:00
Emil J	9f7040b3d1	Merge pull request #4683 from keszybz/use-SOURCE_DATE_EPOCH ... Respect $SOURCE_DATE_EPOCH in generate_bram_types_sim.py	2025-01-10 23:43:26 +01:00
Emil J. Tywoniak	b9b9515bb0	hashlib: hash_eat -> hash_into	2024-12-18 15:09:25 +01:00
Emil J. Tywoniak	4e29ec1854	hashlib: acc -> eat	2024-12-18 15:09:25 +01:00
Emil J. Tywoniak	d071489ab1	hashlib: redo interface for flexibility	2024-12-18 14:49:25 +01:00
Miodrag Milanović	f4ddbc3994	Merge pull request #4771 from pepijndevos/famxtra ... gowin: split cells_xtra by family	2024-12-08 19:46:36 +01:00
KrystalDelusion	c96d02b204	Merge pull request #4784 from YosysHQ/krys/reduce_warnings ... Reduce number of warnings	2024-12-05 09:16:06 +13:00
Emil J	61a6567b9f	Merge pull request #4789 from YosysHQ/emil/sklansky-adder ... Add a Sklansky option for `$lcu` mapping	2024-12-03 11:33:13 +01:00
Emil J. Tywoniak	fe64a714a9	techmap: add a Sklansky option for `$lcu` mapping	2024-12-02 11:34:58 +01:00
Emil J. Tywoniak	ebd7f2b366	techlibs: add _TECHMAP_DO_ to Han-Carlson adder	2024-12-02 09:54:24 +01:00
Krystine Sherwin	1de5d98ae2	Reduce comparisons of size_t and int ... `Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`. For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.	2024-11-29 12:53:29 +13:00
Emil J. Tywoniak	4bf3677640	techmap: set Han-Carlson adder priority consistent with Kogge-Stone	2024-11-28 23:54:00 +01:00
Emil J. Tywoniak	6c78bd3637	techmap: add a Han-Carlson option for `$lcu` mapping	2024-11-28 15:33:21 +01:00
Pepijn de Vos	be836f4af3	gowin: split cells_xtra by family	2024-11-26 15:42:22 +01:00
Emil J	88abc4c20f	Merge pull request #4755 from pepijndevos/cells_xtra ... Gowin: add GW2A and GW5A cells	2024-11-20 13:32:30 +01:00
Pepijn de Vos	b8329df1d0	add GW2A and GW5A cells	2024-11-17 20:25:11 +01:00
Patrick Urban	77e1f748a5	gatemate: run `simplemap` after `muxcover` to prevent unmapped multiplexers	2024-11-15 09:49:49 +01:00
Zbigniew Jędrzejewski-Szmek	26a3478d8d	Drop timestamp in generate_bram_types_sim.py ... I'm working on build reproducibility of Fedora packages, and this patch fixes an issue observed in test rebuilds: the timestamp was set to the actual time of the build, making builds nonreproducible. Other "Generated by" strings do not include a timestamp, so drop it here too.	2024-10-30 08:47:18 +01:00
Krystine Sherwin	27b8b4e81e	Docs: Fix missing groups ... $lut and $sop were missed in the rebase, and $buf is new to main since the last rebase.	2024-10-15 11:08:30 +13:00
Krystine Sherwin	1513366f21	Docs: Adding mux cell descriptions ... Also making ver2 cell descriptions consistently spaced.	2024-10-15 07:37:34 +13:00
Krystine Sherwin	dfe803b5c6	Docs: Comments from @jix ... - Unswap shift/shiftx - Add brief overview to cell lib - Clarify $div cell B input - Clarify unary operators - What is $modfloor	2024-10-15 07:37:20 +13:00
Krystine Sherwin	4d84d7e69f	simlib.v: Add x-output tag ... Also a few extra cell help texts.	2024-10-15 07:35:41 +13:00
Krystine Sherwin	ed92374263	simlib.v: Update case equality operators to v2 ... Also tag as x-aware cells and add titles.	2024-10-15 07:35:41 +13:00
Krystine Sherwin	b1025dbaa6	cellhelp.py: Cells can have tags ... Tags are added to the list of properties when exporting to `cells.json`.	2024-10-15 07:35:41 +13:00
Krystine Sherwin	f70a66f5b3	Docs: Assert cell has group ... Explicitly assign $_TBUF_ to `gate_other` and remove catch if a cell has no group.	2024-10-15 07:35:40 +13:00
Krystine Sherwin	5c4f7b4deb	Docs: $eqx aka case equality	2024-10-15 07:35:40 +13:00
Krystine Sherwin	596d914ead	simcells: Apply group tags	2024-10-15 07:35:40 +13:00
Krystine Sherwin	78b9dbd4ea	Docs: Assign remaining word cells to groups ... Move todos to correct place. Add todo for x-prop cells.	2024-10-15 07:35:40 +13:00
Krystine Sherwin	1374fc2e2b	cellref: Deprecate cell_library.rst ... Most of the word/coarse level cells have an assigned group and individual page. The gate/fine level cells are all on one page. Fix links to `cell_library.rst`.	2024-10-15 07:34:52 +13:00
Krystine Sherwin	04b0ae540d	cellref: Move default help message to register.cc ... Drop the default help message from rst while still displaying it on the command line. Fix command line formatting for older style help messages.	2024-10-15 07:31:47 +13:00
Krystine Sherwin	c662529316	Docs: Move binary operators to cell appendix ... Add binary group tag to relevant cells. Remove content from `cell_library.rst` that is already moved.	2024-10-15 07:31:47 +13:00
Krystine Sherwin	7c5b10fe50	cellref: Add json dump ... New `help -dump-cells-json <file>` to dump cells list. Add 'group' field to SimHelper class/struct with defaults to gate_other and word_other depending on source (simcells or simlib). Add 'unary' group to unary operator cells for testing (based on internal cell library docs page).	2024-10-15 07:25:27 +13:00
Krystine Sherwin	06e5e18371	simlib.v: Autolink referenced cells in alu	2024-10-15 07:23:45 +13:00
Krystine Sherwin	21747c468c	Docs: Improve cell_help usage ... - Drop `cell_code` and instead map code lookups to the `cell_help` dict. - Add helper functions to struct for checking and getting the right cell. - Add `CellType` for cell to `write_cell_rst` function declaration in preparation for use in future. - Iterate over `yosys_celltypes.cell_types` when exporting cell rst files, reporting errors for any cells defined in `cell_types` but not `cell_help_messages`.	2024-10-15 07:23:45 +13:00
Krystine Sherwin	57cd8d29db	cellhelp: Add default format parse for simcells ... Since `simcells.v` uses consistent formatting we can handle it specifically to help tidy up sphinx warnings about the truth tables, and instead chuck them in a code block which when printing to rst. Also has the side effect that rst code blocks can be added manually with `//- ::` followed by a blank line.	2024-10-15 07:16:40 +13:00
Krystine Sherwin	a2b2904ed8	cellhelp: Add source line to help ... Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump. Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.	2024-10-15 07:16:40 +13:00
Krystine Sherwin	784292626e	cellhelp: Rename short_desc to title	2024-10-15 07:16:39 +13:00
Krystine Sherwin	4662476ec8	Docs: Test $alu with v2 help format	2024-10-15 07:16:39 +13:00