mirror of https://github.com/YosysHQ/yosys.git
rtlil: represent Const strings as std::string
This commit is contained in:
parent
61ed9b6263
commit
785bd44da7
4
Makefile
4
Makefile
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@ -930,8 +930,8 @@ ystests: $(TARGETS) $(EXTRA_TARGETS)
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# Unit test
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unit-test: libyosys.so
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@$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CPPFLAGS="$(CPPFLAGS)" \
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CXXFLAGS="$(CXXFLAGS)" LIBS="$(LIBS)" ROOTPATH="$(CURDIR)"
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@$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CC="$(CC)" CPPFLAGS="$(CPPFLAGS)" \
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CXXFLAGS="$(CXXFLAGS)" LINKFLAGS="$(LINKFLAGS)" LIBS="$(LIBS)" ROOTPATH="$(CURDIR)"
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clean-unit-test:
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@$(MAKE) -C $(UNITESTPATH) clean
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@ -387,7 +387,7 @@ struct BlifDumper
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auto &inputs = cell->getPort(ID::A);
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auto width = cell->parameters.at(ID::WIDTH).as_int();
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auto depth = cell->parameters.at(ID::DEPTH).as_int();
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vector<State> table = cell->parameters.at(ID::TABLE).bits;
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vector<State> table = cell->parameters.at(ID::TABLE).to_bits();
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while (GetSize(table) < 2*width*depth)
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table.push_back(State::S0);
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log_assert(inputs.size() == width);
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@ -711,9 +711,9 @@ struct BtorWorker
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Const initval;
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for (int i = 0; i < GetSize(sig_q); i++)
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if (initbits.count(sig_q[i]))
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initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
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initval.bits().push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
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else
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initval.bits.push_back(State::Sx);
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initval.bits().push_back(State::Sx);
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int nid_init_val = -1;
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@ -1042,7 +1042,7 @@ struct BtorWorker
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Const c(bit.data);
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while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr)
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c.bits.push_back(sig[i+GetSize(c)].data);
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c.bits().push_back(sig[i+GetSize(c)].data);
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if (consts.count(c) == 0) {
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int sid = get_bv_sid(GetSize(c));
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@ -328,7 +328,7 @@ struct FlowGraph {
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node_comb_defs[node].insert(chunk.wire);
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}
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}
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for (auto bit : sig.bits())
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for (auto bit : sig)
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bit_has_state[bit] |= is_ff;
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// Only comb defs of an entire wire in the right order can be inlined.
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if (!is_ff && sig.is_wire()) {
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@ -864,7 +864,7 @@ struct CxxrtlWorker {
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if (!module->has_attribute(ID(cxxrtl_template)))
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return {};
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if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING)
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if (!(module->attributes.at(ID(cxxrtl_template)).flags & RTLIL::CONST_FLAG_STRING))
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log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module));
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std::vector<std::string> param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t");
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@ -1665,15 +1665,15 @@ struct CxxrtlWorker {
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switch (bit) {
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case RTLIL::S0:
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case RTLIL::S1:
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compare_mask.bits.push_back(RTLIL::S1);
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compare_value.bits.push_back(bit);
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compare_mask.bits().push_back(RTLIL::S1);
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compare_value.bits().push_back(bit);
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break;
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case RTLIL::Sx:
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case RTLIL::Sz:
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case RTLIL::Sa:
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compare_mask.bits.push_back(RTLIL::S0);
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compare_value.bits.push_back(RTLIL::S0);
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compare_mask.bits().push_back(RTLIL::S0);
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compare_value.bits().push_back(RTLIL::S0);
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break;
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default:
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@ -3028,7 +3028,7 @@ struct CxxrtlWorker {
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if (init == RTLIL::Const()) {
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init = RTLIL::Const(State::Sx, GetSize(bit.wire));
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}
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init[bit.offset] = port.init_value[i];
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init.bits()[bit.offset] = port.init_value[i];
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}
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}
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}
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@ -334,20 +334,20 @@ struct EdifBackend : public Backend {
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auto add_prop = [&](IdString name, Const val) {
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if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0)
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*f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str());
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else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
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else if (val.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
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*f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int());
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else {
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std::string hex_string = "";
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for (size_t i = 0; i < val.bits.size(); i += 4) {
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for (size_t i = 0; i < val.size(); i += 4) {
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int digit_value = 0;
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if (i+0 < val.bits.size() && val.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
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if (i+1 < val.bits.size() && val.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
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if (i+2 < val.bits.size() && val.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
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if (i+3 < val.bits.size() && val.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
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if (i+0 < val.size() && val.at(i+0) == RTLIL::State::S1) digit_value |= 1;
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if (i+1 < val.size() && val.at(i+1) == RTLIL::State::S1) digit_value |= 2;
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if (i+2 < val.size() && val.at(i+2) == RTLIL::State::S1) digit_value |= 4;
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if (i+3 < val.size() && val.at(i+3) == RTLIL::State::S1) digit_value |= 8;
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char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
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hex_string = std::string(digit_str) + hex_string;
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}
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*f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str());
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*f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val), hex_string.c_str());
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}
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};
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for (auto module : sorted_modules)
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@ -149,7 +149,7 @@ std::string dump_const(const RTLIL::Const &data)
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// Numeric (non-real) parameter.
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else
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{
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int width = data.bits.size();
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int width = data.size();
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// If a standard 32-bit int, then emit standard int value like "56" or
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// "-56". Firrtl supports negative-valued int literals.
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@ -163,7 +163,7 @@ std::string dump_const(const RTLIL::Const &data)
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for (int i = 0; i < width; i++)
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{
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switch (data.bits[i])
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switch (data[i])
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{
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case State::S0: break;
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case State::S1: int_val |= (1 << i); break;
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@ -205,7 +205,7 @@ std::string dump_const(const RTLIL::Const &data)
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for (int i = width - 1; i >= 0; i--)
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{
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log_assert(i < width);
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switch (data.bits[i])
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switch (data[i])
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{
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case State::S0: res_str += "0"; break;
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case State::S1: res_str += "1"; break;
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@ -105,7 +105,7 @@ struct MemContentsTest {
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RTLIL::Const values;
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for(addr_t addr = low; addr <= high; addr++) {
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RTLIL::Const word(data_dist(rnd), data_width);
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values.bits.insert(values.bits.end(), word.bits.begin(), word.bits.end());
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values.bits().insert(values.bits().end(), word.begin(), word.end());
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}
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insert_concatenated(low, values);
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}
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@ -176,11 +176,11 @@ struct IntersynthBackend : public Backend {
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}
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}
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for (auto ¶m : cell->parameters) {
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celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), log_id(param.first));
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if (param.second.bits.size() != 32) {
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celltype_code += stringf(" cfg:%d %s", int(param.second.size()), log_id(param.first));
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if (param.second.size() != 32) {
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node_code += stringf(" %s '", log_id(param.first));
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for (int i = param.second.bits.size()-1; i >= 0; i--)
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node_code += param.second.bits[i] == State::S1 ? "1" : "0";
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for (int i = param.second.size()-1; i >= 0; i--)
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node_code += param.second[i] == State::S1 ? "1" : "0";
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} else
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node_code += stringf(" %s 0x%x", log_id(param.first), param.second.as_int());
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}
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@ -33,13 +33,13 @@ YOSYS_NAMESPACE_BEGIN
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void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint)
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{
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if (width < 0)
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width = data.bits.size() - offset;
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if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
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width = data.size() - offset;
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if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.size()) {
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if (width == 32 && autoint) {
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int32_t val = 0;
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for (int i = 0; i < width; i++) {
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log_assert(offset+i < (int)data.bits.size());
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switch (data.bits[offset+i]) {
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log_assert(offset+i < (int)data.size());
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switch (data[offset+i]) {
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case State::S0: break;
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case State::S1: val |= 1 << i; break;
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default: val = -1; break;
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@ -58,8 +58,8 @@ void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi
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f << "x";
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} else {
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for (int i = offset+width-1; i >= offset; i--) {
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log_assert(i < (int)data.bits.size());
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switch (data.bits[i]) {
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log_assert(i < (int)data.size());
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switch (data[i]) {
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case State::S0: f << stringf("0"); break;
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case State::S1: f << stringf("1"); break;
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case RTLIL::Sx: f << stringf("x"); break;
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@ -657,7 +657,7 @@ struct SimplecWorker
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{
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SigSpec sig = sigmaps.at(module)(w);
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Const val = w->attributes.at(ID::init);
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val.bits.resize(GetSize(sig), State::Sx);
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val.bits().resize(GetSize(sig), State::Sx);
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for (int i = 0; i < GetSize(sig); i++)
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if (val[i] == State::S0 || val[i] == State::S1) {
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@ -1077,14 +1077,14 @@ struct Smt2Worker
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RTLIL::SigSpec sig = sigmap(wire);
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Const val = wire->attributes.at(ID::init);
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val.bits.resize(GetSize(sig), State::Sx);
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val.bits().resize(GetSize(sig), State::Sx);
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if (bvmode && GetSize(sig) > 1) {
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Const mask(State::S1, GetSize(sig));
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bool use_mask = false;
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for (int i = 0; i < GetSize(sig); i++)
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if (val[i] != State::S0 && val[i] != State::S1) {
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val[i] = State::S0;
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mask[i] = State::S0;
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val.bits()[i] = State::S0;
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mask.bits()[i] = State::S0;
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use_mask = true;
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}
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if (use_mask)
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@ -1359,10 +1359,10 @@ struct Smt2Worker
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for (int k = 0; k < GetSize(initword); k++) {
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if (initword[k] == State::S0 || initword[k] == State::S1) {
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gen_init_constr = true;
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initmask[k] = State::S1;
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initmask.bits()[k] = State::S1;
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} else {
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initmask[k] = State::S0;
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initword[k] = State::S0;
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initmask.bits()[k] = State::S0;
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initword.bits()[k] = State::S0;
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}
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}
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@ -191,7 +191,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
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{
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bool set_signed = (data.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
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if (width < 0)
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width = data.bits.size() - offset;
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width = data.size() - offset;
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if (width == 0) {
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// See IEEE 1364-2005 Clause 5.1.14.
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f << "{0{1'b0}}";
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@ -199,14 +199,14 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
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}
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if (nostr)
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goto dump_hex;
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if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
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if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.size()) {
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if (width == 32 && !no_decimal && !nodec) {
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int32_t val = 0;
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for (int i = offset+width-1; i >= offset; i--) {
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log_assert(i < (int)data.bits.size());
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if (data.bits[i] != State::S0 && data.bits[i] != State::S1)
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log_assert(i < (int)data.size());
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if (data[i] != State::S0 && data[i] != State::S1)
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goto dump_hex;
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if (data.bits[i] == State::S1)
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if (data[i] == State::S1)
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val |= 1 << (i - offset);
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}
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if (decimal)
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@ -221,8 +221,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
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goto dump_bin;
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vector<char> bin_digits, hex_digits;
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for (int i = offset; i < offset+width; i++) {
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log_assert(i < (int)data.bits.size());
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switch (data.bits[i]) {
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log_assert(i < (int)data.size());
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switch (data[i]) {
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case State::S0: bin_digits.push_back('0'); break;
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case State::S1: bin_digits.push_back('1'); break;
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case RTLIL::Sx: bin_digits.push_back('x'); break;
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@ -275,8 +275,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
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if (width == 0)
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f << stringf("0");
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for (int i = offset+width-1; i >= offset; i--) {
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log_assert(i < (int)data.bits.size());
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switch (data.bits[i]) {
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log_assert(i < (int)data.size());
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switch (data[i]) {
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case State::S0: f << stringf("0"); break;
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case State::S1: f << stringf("1"); break;
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case RTLIL::Sx: f << stringf("x"); break;
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@ -318,10 +318,10 @@ void dump_reg_init(std::ostream &f, SigSpec sig)
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for (auto bit : active_sigmap(sig)) {
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if (active_initdata.count(bit)) {
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initval.bits.push_back(active_initdata.at(bit));
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initval.bits().push_back(active_initdata.at(bit));
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gotinit = true;
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} else {
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initval.bits.push_back(State::Sx);
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initval.bits().push_back(State::Sx);
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}
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}
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@ -751,7 +751,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
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if (port.wide_log2) {
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Const addr_lo;
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for (int i = 0; i < port.wide_log2; i++)
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addr_lo.bits.push_back(State(sub >> i & 1));
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addr_lo.bits().push_back(State(sub >> i & 1));
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os << "{";
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os << temp_id;
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os << ", ";
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@ -448,7 +448,7 @@ void AigerReader::parse_xaiger()
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bool success = ce.eval(o);
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log_assert(success);
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log_assert(o.wire == nullptr);
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lut_mask[gray] = o.data;
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lut_mask.bits()[gray] = o.data;
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}
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RTLIL::Cell *output_cell = module->cell(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID));
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log_assert(output_cell);
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@ -951,15 +951,7 @@ RTLIL::Const AstNode::asAttrConst() const
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{
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log_assert(type == AST_CONSTANT);
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RTLIL::Const val;
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val.bits = bits;
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if (is_string) {
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val.flags |= RTLIL::CONST_FLAG_STRING;
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log_assert(val.decode_string() == str);
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}
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return val;
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return is_string ? RTLIL::Const(str) : RTLIL::Const(bits);
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}
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RTLIL::Const AstNode::asParaConst() const
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@ -1005,7 +997,7 @@ uint64_t AstNode::asInt(bool is_signed)
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uint64_t ret = 0;
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for (int i = 0; i < 64; i++)
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if (v.bits.at(i) == RTLIL::State::S1)
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if (v.at(i) == RTLIL::State::S1)
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ret |= uint64_t(1) << i;
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return ret;
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@ -1023,15 +1015,15 @@ double AstNode::asReal(bool is_signed)
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{
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RTLIL::Const val(bits);
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bool is_negative = is_signed && !val.bits.empty() && val.bits.back() == RTLIL::State::S1;
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bool is_negative = is_signed && !val.empty() && val.back() == RTLIL::State::S1;
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if (is_negative)
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val = const_neg(val, val, false, false, val.bits.size());
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val = const_neg(val, val, false, false, val.size());
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double v = 0;
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for (size_t i = 0; i < val.bits.size(); i++)
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for (size_t i = 0; i < val.size(); i++)
|
||||
// IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in
|
||||
// the net or the variable shall be treated as zero upon conversion.
|
||||
if (val.bits.at(i) == RTLIL::State::S1)
|
||||
if (val.at(i) == RTLIL::State::S1)
|
||||
v += exp2(i);
|
||||
if (is_negative)
|
||||
v *= -1;
|
||||
|
@ -1054,15 +1046,15 @@ RTLIL::Const AstNode::realAsConst(int width)
|
|||
#else
|
||||
if (!std::isfinite(v)) {
|
||||
#endif
|
||||
result.bits = std::vector<RTLIL::State>(width, RTLIL::State::Sx);
|
||||
result = std::vector<RTLIL::State>(width, RTLIL::State::Sx);
|
||||
} else {
|
||||
bool is_negative = v < 0;
|
||||
if (is_negative)
|
||||
v *= -1;
|
||||
for (int i = 0; i < width; i++, v /= 2)
|
||||
result.bits.push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
result.bits().push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
if (is_negative)
|
||||
result = const_neg(result, result, false, false, result.bits.size());
|
||||
result = const_neg(result, result, false, false, result.size());
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
@ -1767,16 +1759,7 @@ static std::string serialize_param_value(const RTLIL::Const &val) {
|
|||
res.push_back('r');
|
||||
res += stringf("%d", GetSize(val));
|
||||
res.push_back('\'');
|
||||
for (int i = GetSize(val) - 1; i >= 0; i--) {
|
||||
switch (val.bits[i]) {
|
||||
case RTLIL::State::S0: res.push_back('0'); break;
|
||||
case RTLIL::State::S1: res.push_back('1'); break;
|
||||
case RTLIL::State::Sx: res.push_back('x'); break;
|
||||
case RTLIL::State::Sz: res.push_back('z'); break;
|
||||
case RTLIL::State::Sa: res.push_back('?'); break;
|
||||
case RTLIL::State::Sm: res.push_back('m'); break;
|
||||
}
|
||||
}
|
||||
res.append(val.as_string("?"));
|
||||
return res;
|
||||
}
|
||||
|
||||
|
@ -1868,7 +1851,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
|
|||
} else if ((it->second.flags & RTLIL::CONST_FLAG_STRING) != 0)
|
||||
child->children[0] = AstNode::mkconst_str(it->second.decode_string());
|
||||
else
|
||||
child->children[0] = AstNode::mkconst_bits(it->second.bits, (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0);
|
||||
child->children[0] = AstNode::mkconst_bits(it->second.to_bits(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0);
|
||||
rewritten.insert(it->first);
|
||||
}
|
||||
|
||||
|
@ -1881,7 +1864,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
|
|||
if ((param.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
|
||||
defparam->children.push_back(AstNode::mkconst_str(param.second.decode_string()));
|
||||
else
|
||||
defparam->children.push_back(AstNode::mkconst_bits(param.second.bits, (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0));
|
||||
defparam->children.push_back(AstNode::mkconst_bits(param.second.to_bits(), (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0));
|
||||
new_ast->children.push_back(defparam);
|
||||
}
|
||||
|
||||
|
|
|
@ -735,10 +735,10 @@ struct AST_INTERNAL::ProcessGenerator
|
|||
for (auto sync : proc->syncs) {
|
||||
if (sync->type == RTLIL::STp) {
|
||||
triggers.append(sync->signal);
|
||||
polarity.bits.push_back(RTLIL::S1);
|
||||
polarity.bits().push_back(RTLIL::S1);
|
||||
} else if (sync->type == RTLIL::STn) {
|
||||
triggers.append(sync->signal);
|
||||
polarity.bits.push_back(RTLIL::S0);
|
||||
polarity.bits().push_back(RTLIL::S0);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -832,10 +832,10 @@ struct AST_INTERNAL::ProcessGenerator
|
|||
for (auto sync : proc->syncs) {
|
||||
if (sync->type == RTLIL::STp) {
|
||||
triggers.append(sync->signal);
|
||||
polarity.bits.push_back(RTLIL::S1);
|
||||
polarity.bits().push_back(RTLIL::S1);
|
||||
} else if (sync->type == RTLIL::STn) {
|
||||
triggers.append(sync->signal);
|
||||
polarity.bits.push_back(RTLIL::S0);
|
||||
polarity.bits().push_back(RTLIL::S0);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -892,7 +892,7 @@ struct AST_INTERNAL::ProcessGenerator
|
|||
RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx);
|
||||
for (int i = 0; i < portid; i++) {
|
||||
int new_bit = port_map[std::make_pair(memid, i)];
|
||||
priority_mask.bits[new_bit] = orig_priority_mask.bits[i];
|
||||
priority_mask.bits()[new_bit] = orig_priority_mask[i];
|
||||
}
|
||||
action.priority_mask = priority_mask;
|
||||
sync->mem_write_actions.push_back(action);
|
||||
|
|
|
@ -1718,8 +1718,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
|
|||
if (v->type == AST_CONSTANT && v->bits_only_01()) {
|
||||
RTLIL::Const case_item_expr = v->bitsAsConst(width_hint, sign_hint);
|
||||
RTLIL::Const match = const_eq(case_expr, case_item_expr, sign_hint, sign_hint, 1);
|
||||
log_assert(match.bits.size() == 1);
|
||||
if (match.bits.front() == RTLIL::State::S1) {
|
||||
log_assert(match.size() == 1);
|
||||
if (match.front() == RTLIL::State::S1) {
|
||||
while (i+1 < GetSize(children))
|
||||
delete children[++i];
|
||||
goto keep_const_cond;
|
||||
|
@ -2021,7 +2021,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
|
|||
if (children[1]->type != AST_CONSTANT)
|
||||
input_error("Right operand of to_bits expression is not constant!\n");
|
||||
RTLIL::Const new_value = children[1]->bitsAsConst(children[0]->bitsAsConst().as_int(), children[1]->is_signed);
|
||||
newNode = mkconst_bits(new_value.bits, children[1]->is_signed);
|
||||
newNode = mkconst_bits(new_value.to_bits(), children[1]->is_signed);
|
||||
goto apply_newNode;
|
||||
}
|
||||
|
||||
|
@ -2184,7 +2184,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
|
|||
log_file_warning(filename, location.first_line, "converting real value %e to binary %s.\n",
|
||||
children[0]->realvalue, log_signal(constvalue));
|
||||
delete children[0];
|
||||
children[0] = mkconst_bits(constvalue.bits, sign_hint);
|
||||
children[0] = mkconst_bits(constvalue.to_bits(), sign_hint);
|
||||
fixup_hierarchy_flags();
|
||||
did_something = true;
|
||||
}
|
||||
|
@ -2193,7 +2193,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
|
|||
RTLIL::SigSpec sig(children[0]->bits);
|
||||
sig.extend_u0(width, children[0]->is_signed);
|
||||
AstNode *old_child_0 = children[0];
|
||||
children[0] = mkconst_bits(sig.as_const().bits, is_signed);
|
||||
children[0] = mkconst_bits(sig.as_const().to_bits(), is_signed);
|
||||
delete old_child_0;
|
||||
fixup_hierarchy_flags();
|
||||
}
|
||||
|
@ -3493,8 +3493,8 @@ skip_dynamic_range_lvalue_expansion:;
|
|||
delete buf;
|
||||
|
||||
uint32_t result = 0;
|
||||
for (size_t i = 0; i < arg_value.bits.size(); i++)
|
||||
if (arg_value.bits.at(i) == RTLIL::State::S1)
|
||||
for (size_t i = 0; i < arg_value.size(); i++)
|
||||
if (arg_value.at(i) == RTLIL::State::S1)
|
||||
result = i + 1;
|
||||
|
||||
newNode = mkconst_int(result, true);
|
||||
|
@ -4173,14 +4173,14 @@ replace_fcall_later:;
|
|||
case AST_BIT_NOT:
|
||||
if (children[0]->type == AST_CONSTANT) {
|
||||
RTLIL::Const y = RTLIL::const_not(children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint);
|
||||
newNode = mkconst_bits(y.bits, sign_hint);
|
||||
newNode = mkconst_bits(y.to_bits(), sign_hint);
|
||||
}
|
||||
break;
|
||||
case AST_TO_SIGNED:
|
||||
case AST_TO_UNSIGNED:
|
||||
if (children[0]->type == AST_CONSTANT) {
|
||||
RTLIL::Const y = children[0]->bitsAsConst(width_hint, sign_hint);
|
||||
newNode = mkconst_bits(y.bits, type == AST_TO_SIGNED);
|
||||
newNode = mkconst_bits(y.to_bits(), type == AST_TO_SIGNED);
|
||||
}
|
||||
break;
|
||||
if (0) { case AST_BIT_AND: const_func = RTLIL::const_and; }
|
||||
|
@ -4190,7 +4190,7 @@ replace_fcall_later:;
|
|||
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
|
||||
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
|
||||
children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint);
|
||||
newNode = mkconst_bits(y.bits, sign_hint);
|
||||
newNode = mkconst_bits(y.to_bits(), sign_hint);
|
||||
}
|
||||
break;
|
||||
if (0) { case AST_REDUCE_AND: const_func = RTLIL::const_reduce_and; }
|
||||
|
@ -4200,13 +4200,13 @@ replace_fcall_later:;
|
|||
if (0) { case AST_REDUCE_BOOL: const_func = RTLIL::const_reduce_bool; }
|
||||
if (children[0]->type == AST_CONSTANT) {
|
||||
RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), dummy_arg, false, false, -1);
|
||||
newNode = mkconst_bits(y.bits, false);
|
||||
newNode = mkconst_bits(y.to_bits(), false);
|
||||
}
|
||||
break;
|
||||
case AST_LOGIC_NOT:
|
||||
if (children[0]->type == AST_CONSTANT) {
|
||||
RTLIL::Const y = RTLIL::const_logic_not(RTLIL::Const(children[0]->bits), dummy_arg, children[0]->is_signed, false, -1);
|
||||
newNode = mkconst_bits(y.bits, false);
|
||||
newNode = mkconst_bits(y.to_bits(), false);
|
||||
} else
|
||||
if (children[0]->isConst()) {
|
||||
newNode = mkconst_int(children[0]->asReal(sign_hint) == 0, false, 1);
|
||||
|
@ -4217,7 +4217,7 @@ replace_fcall_later:;
|
|||
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
|
||||
RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), RTLIL::Const(children[1]->bits),
|
||||
children[0]->is_signed, children[1]->is_signed, -1);
|
||||
newNode = mkconst_bits(y.bits, false);
|
||||
newNode = mkconst_bits(y.to_bits(), false);
|
||||
} else
|
||||
if (children[0]->isConst() && children[1]->isConst()) {
|
||||
if (type == AST_LOGIC_AND)
|
||||
|
@ -4234,7 +4234,7 @@ replace_fcall_later:;
|
|||
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
|
||||
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
|
||||
RTLIL::Const(children[1]->bits), sign_hint, type == AST_POW ? children[1]->is_signed : false, width_hint);
|
||||
newNode = mkconst_bits(y.bits, sign_hint);
|
||||
newNode = mkconst_bits(y.to_bits(), sign_hint);
|
||||
} else
|
||||
if (type == AST_POW && children[0]->isConst() && children[1]->isConst()) {
|
||||
newNode = new AstNode(AST_REALVALUE);
|
||||
|
@ -4254,7 +4254,7 @@ replace_fcall_later:;
|
|||
bool cmp_signed = children[0]->is_signed && children[1]->is_signed;
|
||||
RTLIL::Const y = const_func(children[0]->bitsAsConst(cmp_width, cmp_signed),
|
||||
children[1]->bitsAsConst(cmp_width, cmp_signed), cmp_signed, cmp_signed, 1);
|
||||
newNode = mkconst_bits(y.bits, false);
|
||||
newNode = mkconst_bits(y.to_bits(), false);
|
||||
} else
|
||||
if (children[0]->isConst() && children[1]->isConst()) {
|
||||
bool cmp_signed = (children[0]->type == AST_REALVALUE || children[0]->is_signed) && (children[1]->type == AST_REALVALUE || children[1]->is_signed);
|
||||
|
@ -4279,7 +4279,7 @@ replace_fcall_later:;
|
|||
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
|
||||
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
|
||||
children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint);
|
||||
newNode = mkconst_bits(y.bits, sign_hint);
|
||||
newNode = mkconst_bits(y.to_bits(), sign_hint);
|
||||
} else
|
||||
if (children[0]->isConst() && children[1]->isConst()) {
|
||||
newNode = new AstNode(AST_REALVALUE);
|
||||
|
@ -4298,7 +4298,7 @@ replace_fcall_later:;
|
|||
if (0) { case AST_NEG: const_func = RTLIL::const_neg; }
|
||||
if (children[0]->type == AST_CONSTANT) {
|
||||
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint);
|
||||
newNode = mkconst_bits(y.bits, sign_hint);
|
||||
newNode = mkconst_bits(y.to_bits(), sign_hint);
|
||||
} else
|
||||
if (children[0]->isConst()) {
|
||||
newNode = new AstNode(AST_REALVALUE);
|
||||
|
@ -4326,10 +4326,10 @@ replace_fcall_later:;
|
|||
newNode->realvalue = choice->asReal(sign_hint);
|
||||
} else {
|
||||
RTLIL::Const y = choice->bitsAsConst(width_hint, sign_hint);
|
||||
if (choice->is_string && y.bits.size() % 8 == 0 && sign_hint == false)
|
||||
newNode = mkconst_str(y.bits);
|
||||
if (choice->is_string && y.size() % 8 == 0 && sign_hint == false)
|
||||
newNode = mkconst_str(y.to_bits());
|
||||
else
|
||||
newNode = mkconst_bits(y.bits, sign_hint);
|
||||
newNode = mkconst_bits(y.to_bits(), sign_hint);
|
||||
}
|
||||
} else
|
||||
if (choice->isConst()) {
|
||||
|
@ -4338,11 +4338,11 @@ replace_fcall_later:;
|
|||
} else if (children[1]->type == AST_CONSTANT && children[2]->type == AST_CONSTANT) {
|
||||
RTLIL::Const a = children[1]->bitsAsConst(width_hint, sign_hint);
|
||||
RTLIL::Const b = children[2]->bitsAsConst(width_hint, sign_hint);
|
||||
log_assert(a.bits.size() == b.bits.size());
|
||||
for (size_t i = 0; i < a.bits.size(); i++)
|
||||
if (a.bits[i] != b.bits[i])
|
||||
a.bits[i] = RTLIL::State::Sx;
|
||||
newNode = mkconst_bits(a.bits, sign_hint);
|
||||
log_assert(a.size() == b.size());
|
||||
for (size_t i = 0; i < a.size(); i++)
|
||||
if (a[i] != b[i])
|
||||
a.bits()[i] = RTLIL::State::Sx;
|
||||
newNode = mkconst_bits(a.to_bits(), sign_hint);
|
||||
} else if (children[1]->isConst() && children[2]->isConst()) {
|
||||
newNode = new AstNode(AST_REALVALUE);
|
||||
if (children[1]->asReal(sign_hint) == children[2]->asReal(sign_hint))
|
||||
|
@ -4363,7 +4363,7 @@ replace_fcall_later:;
|
|||
val = children[1]->bitsAsUnsizedConst(width);
|
||||
else
|
||||
val = children[1]->bitsAsConst(width);
|
||||
newNode = mkconst_bits(val.bits, children[1]->is_signed);
|
||||
newNode = mkconst_bits(val.to_bits(), children[1]->is_signed);
|
||||
}
|
||||
break;
|
||||
case AST_CONCAT:
|
||||
|
@ -4948,7 +4948,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
|
|||
target->str = str;
|
||||
target->id2ast = id2ast;
|
||||
target->was_checked = true;
|
||||
block->children.push_back(new AstNode(AST_ASSIGN_EQ, target, mkconst_bits(data.extract(i*wordsz + pos, clen).bits, false)));
|
||||
block->children.push_back(new AstNode(AST_ASSIGN_EQ, target, mkconst_bits(data.extract(i*wordsz + pos, clen).to_bits(), false)));
|
||||
pos = epos;
|
||||
}
|
||||
}
|
||||
|
@ -5303,7 +5303,7 @@ bool AstNode::is_simple_const_expr()
|
|||
bool AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &variables, AstNode *fcall, bool must_succeed)
|
||||
{
|
||||
if (type == AST_IDENTIFIER && variables.count(str)) {
|
||||
int offset = variables.at(str).offset, width = variables.at(str).val.bits.size();
|
||||
int offset = variables.at(str).offset, width = variables.at(str).val.size();
|
||||
if (!children.empty()) {
|
||||
if (children.size() != 1 || children.at(0)->type != AST_RANGE) {
|
||||
if (!must_succeed)
|
||||
|
@ -5326,7 +5326,7 @@ bool AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia
|
|||
offset -= variables.at(str).offset;
|
||||
if (variables.at(str).range_swapped)
|
||||
offset = -offset;
|
||||
std::vector<RTLIL::State> &var_bits = variables.at(str).val.bits;
|
||||
std::vector<RTLIL::State> &var_bits = variables.at(str).val.bits();
|
||||
std::vector<RTLIL::State> new_bits(var_bits.begin() + offset, var_bits.begin() + offset + width);
|
||||
AstNode *newNode = mkconst_bits(new_bits, variables.at(str).is_signed);
|
||||
newNode->cloneInto(this);
|
||||
|
@ -5457,7 +5457,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
|
|||
}
|
||||
|
||||
if (stmt->children.at(0)->children.empty()) {
|
||||
variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size());
|
||||
variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.size());
|
||||
} else {
|
||||
AstNode *range = stmt->children.at(0)->children.at(0);
|
||||
if (!range->range_valid) {
|
||||
|
@ -5468,12 +5468,12 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
|
|||
int offset = min(range->range_left, range->range_right);
|
||||
int width = std::abs(range->range_left - range->range_right) + 1;
|
||||
varinfo_t &v = variables[stmt->children.at(0)->str];
|
||||
RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.bits.size());
|
||||
RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.size());
|
||||
for (int i = 0; i < width; i++) {
|
||||
int index = i + offset - v.offset;
|
||||
if (v.range_swapped)
|
||||
index = -index;
|
||||
v.val.bits.at(index) = r.bits.at(i);
|
||||
v.val.bits().at(index) = r.at(i);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -5616,7 +5616,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
|
|||
log_abort();
|
||||
}
|
||||
|
||||
result = AstNode::mkconst_bits(variables.at(str).val.bits, variables.at(str).is_signed);
|
||||
result = AstNode::mkconst_bits(variables.at(str).val.to_bits(), variables.at(str).is_signed);
|
||||
|
||||
finished:
|
||||
delete block;
|
||||
|
|
|
@ -149,7 +149,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
|
|||
if (buffer[0] == '.')
|
||||
{
|
||||
if (lutptr) {
|
||||
for (auto &bit : lutptr->bits)
|
||||
for (auto &bit : lutptr->bits())
|
||||
if (bit == RTLIL::State::Sx)
|
||||
bit = lut_default_state;
|
||||
lutptr = NULL;
|
||||
|
@ -321,9 +321,9 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
|
|||
const_v = Const(str);
|
||||
} else {
|
||||
int n = strlen(v);
|
||||
const_v.bits.resize(n);
|
||||
const_v.bits().resize(n);
|
||||
for (int i = 0; i < n; i++)
|
||||
const_v.bits[i] = v[n-i-1] != '0' ? State::S1 : State::S0;
|
||||
const_v.bits()[i] = v[n-i-1] != '0' ? State::S1 : State::S0;
|
||||
}
|
||||
if (!strcmp(cmd, ".attr")) {
|
||||
if (obj_attributes == nullptr) {
|
||||
|
@ -566,16 +566,16 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
|
|||
for (int i = 0; i < input_len; i++)
|
||||
switch (input[i]) {
|
||||
case '0':
|
||||
sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
|
||||
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
|
||||
sopcell->parameters[ID::TABLE].bits().push_back(State::S1);
|
||||
sopcell->parameters[ID::TABLE].bits().push_back(State::S0);
|
||||
break;
|
||||
case '1':
|
||||
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
|
||||
sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
|
||||
sopcell->parameters[ID::TABLE].bits().push_back(State::S0);
|
||||
sopcell->parameters[ID::TABLE].bits().push_back(State::S1);
|
||||
break;
|
||||
default:
|
||||
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
|
||||
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
|
||||
sopcell->parameters[ID::TABLE].bits().push_back(State::S0);
|
||||
sopcell->parameters[ID::TABLE].bits().push_back(State::S0);
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -605,7 +605,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
|
|||
goto try_next_value;
|
||||
}
|
||||
}
|
||||
lutptr->bits.at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1;
|
||||
lutptr->bits().at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1;
|
||||
try_next_value:;
|
||||
}
|
||||
|
||||
|
|
|
@ -447,7 +447,7 @@ constant:
|
|||
bits.pop_back();
|
||||
$$ = new RTLIL::Const;
|
||||
for (auto it = bits.begin(); it != bits.end(); it++)
|
||||
$$->bits.push_back(*it);
|
||||
$$->bits().push_back(*it);
|
||||
if (is_signed) {
|
||||
$$->flags |= RTLIL::CONST_FLAG_SIGNED;
|
||||
}
|
||||
|
|
|
@ -236,23 +236,6 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
|
|||
return s;
|
||||
}
|
||||
|
||||
RTLIL::Const mkconst_str(const std::string &str)
|
||||
{
|
||||
RTLIL::Const val;
|
||||
std::vector<RTLIL::State> data;
|
||||
data.reserve(str.size() * 8);
|
||||
for (size_t i = 0; i < str.size(); i++) {
|
||||
unsigned char ch = str[str.size() - i - 1];
|
||||
for (int j = 0; j < 8; j++) {
|
||||
data.push_back((ch & 1) ? State::S1 : State::S0);
|
||||
ch = ch >> 1;
|
||||
}
|
||||
}
|
||||
val.bits = data;
|
||||
val.flags |= RTLIL::CONST_FLAG_STRING;
|
||||
return val;
|
||||
}
|
||||
|
||||
static const RTLIL::Const extract_vhdl_boolean(std::string &val)
|
||||
{
|
||||
if (val == "false")
|
||||
|
@ -295,7 +278,7 @@ static const RTLIL::Const extract_vhdl_char(std::string &val)
|
|||
|
||||
static const RTLIL::Const extract_real_value(std::string &val)
|
||||
{
|
||||
RTLIL::Const c = mkconst_str(val);
|
||||
RTLIL::Const c(val);
|
||||
c.flags |= RTLIL::CONST_FLAG_REAL;
|
||||
return c;
|
||||
}
|
||||
|
@ -333,7 +316,7 @@ static const RTLIL::Const extract_vhdl_const(const char *value, bool output_sig
|
|||
} else if (val == "true") {
|
||||
c = RTLIL::Const::from_string("1");
|
||||
} else {
|
||||
c = mkconst_str(val);
|
||||
c = RTLIL::Const(val);
|
||||
log_warning("encoding value '%s' as string.\n", value);
|
||||
}
|
||||
if (is_signed)
|
||||
|
@ -364,7 +347,7 @@ static const RTLIL::Const extract_verilog_const(const char *value, bool allow_s
|
|||
} else if (allow_string) {
|
||||
c = RTLIL::Const(val);
|
||||
} else {
|
||||
c = mkconst_str(val);
|
||||
c = RTLIL::Const(val);
|
||||
log_warning("encoding value '%s' as string.\n", value);
|
||||
}
|
||||
if (is_signed)
|
||||
|
@ -1634,7 +1617,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
|
|||
if (*ascii_initdata == 0)
|
||||
break;
|
||||
if (*ascii_initdata == '0' || *ascii_initdata == '1') {
|
||||
initval[bit_idx] = (*ascii_initdata == '0') ? State::S0 : State::S1;
|
||||
initval.bits()[bit_idx] = (*ascii_initdata == '0') ? State::S0 : State::S1;
|
||||
initval_valid = true;
|
||||
}
|
||||
ascii_initdata++;
|
||||
|
@ -1756,9 +1739,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
|
|||
|
||||
if (init_nets.count(net)) {
|
||||
if (init_nets.at(net) == '0')
|
||||
initval.bits.at(bitidx) = State::S0;
|
||||
initval.bits().at(bitidx) = State::S0;
|
||||
if (init_nets.at(net) == '1')
|
||||
initval.bits.at(bitidx) = State::S1;
|
||||
initval.bits().at(bitidx) = State::S1;
|
||||
initval_valid = true;
|
||||
init_nets.erase(net);
|
||||
}
|
||||
|
@ -1832,12 +1815,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
|
|||
initval = bit.wire->attributes.at(ID::init);
|
||||
|
||||
while (GetSize(initval) < GetSize(bit.wire))
|
||||
initval.bits.push_back(State::Sx);
|
||||
initval.bits().push_back(State::Sx);
|
||||
|
||||
if (it.second == '0')
|
||||
initval.bits.at(bit.offset) = State::S0;
|
||||
initval.bits().at(bit.offset) = State::S0;
|
||||
if (it.second == '1')
|
||||
initval.bits.at(bit.offset) = State::S1;
|
||||
initval.bits().at(bit.offset) = State::S1;
|
||||
|
||||
bit.wire->attributes[ID::init] = initval;
|
||||
}
|
||||
|
@ -2024,7 +2007,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
|
|||
}
|
||||
|
||||
Const qx_init = Const(State::S1, width);
|
||||
qx_init.bits.resize(2 * width, State::S0);
|
||||
qx_init.bits().resize(2 * width, State::S0);
|
||||
|
||||
clocking.addDff(new_verific_id(inst), sig_dx, sig_qx, qx_init);
|
||||
module->addXnor(new_verific_id(inst), sig_dx, sig_qx, sig_ox);
|
||||
|
@ -2295,7 +2278,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
|
|||
continue;
|
||||
|
||||
if (non_ff_bits.count(SigBit(wire, i)))
|
||||
initval[i] = State::Sx;
|
||||
initval.bits()[i] = State::Sx;
|
||||
}
|
||||
|
||||
if (wire->port_input) {
|
||||
|
@ -2482,7 +2465,7 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const
|
|||
if (c.wire && c.wire->attributes.count(ID::init)) {
|
||||
Const val = c.wire->attributes.at(ID::init);
|
||||
for (int i = 0; i < GetSize(c); i++)
|
||||
initval[offset+i] = val[c.offset+i];
|
||||
initval.bits()[offset+i] = val[c.offset+i];
|
||||
}
|
||||
offset += GetSize(c);
|
||||
}
|
||||
|
@ -2553,7 +2536,7 @@ Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::
|
|||
if (c.wire && c.wire->attributes.count(ID::init)) {
|
||||
Const val = c.wire->attributes.at(ID::init);
|
||||
for (int i = 0; i < GetSize(c); i++)
|
||||
initval[offset+i] = val[c.offset+i];
|
||||
initval.bits()[offset+i] = val[c.offset+i];
|
||||
}
|
||||
offset += GetSize(c);
|
||||
}
|
||||
|
|
|
@ -575,7 +575,7 @@ struct SvaFsm
|
|||
|
||||
if (delta_pos >= 0 && i_within_j && j_within_i) {
|
||||
did_something = true;
|
||||
values[i][delta_pos] = State::Sa;
|
||||
values[i].bits()[delta_pos] = State::Sa;
|
||||
values[j] = values.back();
|
||||
values.pop_back();
|
||||
goto next_pair;
|
||||
|
|
|
@ -80,7 +80,7 @@ struct BitPatternPool
|
|||
bits_t sig2bits(RTLIL::SigSpec sig)
|
||||
{
|
||||
bits_t bits;
|
||||
bits.bitdata = sig.as_const().bits;
|
||||
bits.bitdata = sig.as_const().bits();
|
||||
for (auto &b : bits.bitdata)
|
||||
if (b > RTLIL::State::S1)
|
||||
b = RTLIL::State::Sa;
|
||||
|
|
170
kernel/calc.cc
170
kernel/calc.cc
|
@ -30,13 +30,13 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
|
|||
{
|
||||
RTLIL::State padding = RTLIL::State::S0;
|
||||
|
||||
if (arg.bits.size() > 0 && is_signed)
|
||||
padding = arg.bits.back();
|
||||
if (arg.size() > 0 && is_signed)
|
||||
padding = arg.back();
|
||||
|
||||
while (int(arg.bits.size()) < width)
|
||||
arg.bits.push_back(padding);
|
||||
while (int(arg.size()) < width)
|
||||
arg.bits().push_back(padding);
|
||||
|
||||
arg.bits.resize(width);
|
||||
arg.bits().resize(width);
|
||||
}
|
||||
|
||||
static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
|
||||
|
@ -45,17 +45,17 @@ static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_
|
|||
|
||||
BigInteger::Sign sign = BigInteger::positive;
|
||||
State inv_sign_bit = RTLIL::State::S1;
|
||||
size_t num_bits = val.bits.size();
|
||||
size_t num_bits = val.size();
|
||||
|
||||
if (as_signed && num_bits && val.bits[num_bits-1] == RTLIL::State::S1) {
|
||||
if (as_signed && num_bits && val[num_bits-1] == RTLIL::State::S1) {
|
||||
inv_sign_bit = RTLIL::State::S0;
|
||||
sign = BigInteger::negative;
|
||||
num_bits--;
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < num_bits; i++)
|
||||
if (val.bits[i] == RTLIL::State::S0 || val.bits[i] == RTLIL::State::S1)
|
||||
mag.setBit(i, val.bits[i] == inv_sign_bit);
|
||||
if (val[i] == RTLIL::State::S0 || val[i] == RTLIL::State::S1)
|
||||
mag.setBit(i, val[i] == inv_sign_bit);
|
||||
else if (undef_bit_pos < 0)
|
||||
undef_bit_pos = i;
|
||||
|
||||
|
@ -79,19 +79,19 @@ static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_b
|
|||
{
|
||||
mag--;
|
||||
for (int i = 0; i < result_len; i++)
|
||||
result.bits[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1;
|
||||
result.bits()[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1;
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int i = 0; i < result_len; i++)
|
||||
result.bits[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0;
|
||||
result.bits()[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0;
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (undef_bit_pos >= 0)
|
||||
for (int i = undef_bit_pos; i < result_len; i++)
|
||||
result.bits[i] = RTLIL::State::Sx;
|
||||
result[i] = RTLIL::State::Sx;
|
||||
#endif
|
||||
|
||||
return result;
|
||||
|
@ -132,19 +132,19 @@ static RTLIL::State logic_xnor(RTLIL::State a, RTLIL::State b)
|
|||
RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
|
||||
{
|
||||
if (result_len < 0)
|
||||
result_len = arg1.bits.size();
|
||||
result_len = arg1.size( |