mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4608 from phsauter/rtlil-const-compress
rtlil: add Const::compress helper function
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commit
61ed9b6263
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@ -28,6 +28,7 @@
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#include <string.h>
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#include <algorithm>
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#include <optional>
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YOSYS_NAMESPACE_BEGIN
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@ -280,6 +281,52 @@ int RTLIL::Const::as_int(bool is_signed) const
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return ret;
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}
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size_t RTLIL::Const::get_min_size(bool is_signed) const
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{
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if (bits.empty()) return 0;
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// back to front (MSB to LSB)
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RTLIL::State leading_bit;
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if (is_signed)
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leading_bit = (bits.back() == RTLIL::State::Sx) ? RTLIL::State::S0 : bits.back();
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else
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leading_bit = RTLIL::State::S0;
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size_t idx = bits.size();
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while (idx > 0 && bits[idx -1] == leading_bit) {
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idx--;
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}
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// signed needs one leading bit
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if (is_signed && idx < bits.size()) {
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idx++;
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}
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// must be at least one bit
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return (idx == 0) ? 1 : idx;
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}
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void RTLIL::Const::compress(bool is_signed)
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{
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size_t idx = get_min_size(is_signed);
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bits.erase(bits.begin() + idx, bits.end());
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}
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std::optional<int> RTLIL::Const::as_int_compress(bool is_signed) const
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{
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size_t size = get_min_size(is_signed);
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if(size == 0 || size > 32)
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return std::nullopt;
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int32_t ret = 0;
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for (size_t i = 0; i < size && i < 32; i++)
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if (bits[i] == State::S1)
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ret |= 1 << i;
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if (is_signed && bits[size-1] == State::S1)
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for (size_t i = size; i < 32; i++)
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ret |= 1 << i;
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return ret;
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}
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std::string RTLIL::Const::as_string() const
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{
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std::string ret;
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@ -703,6 +703,14 @@ struct RTLIL::Const
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return ret;
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}
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// find the MSB without redundant leading bits
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size_t get_min_size(bool is_signed) const;
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// compress representation to the minimum required bits
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void compress(bool is_signed = false);
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std::optional<int> as_int_compress(bool is_signed) const;
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void extu(int width) {
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bits.resize(width, RTLIL::State::S0);
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}
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