Benedikt Tutzer
c151bb31eb
Added sample code for python-api
2018-12-11 08:13:42 +01:00
Benedikt Tutzer
6577a69246
throw exception when member is NULL
2018-12-06 12:17:09 +01:00
Benedikt Tutzer
5c59429893
added all variable in __init__.py to allow importing of the whole module
2018-10-25 16:32:28 +02:00
Benedikt Tutzer
0b81629779
changed dlopen flags to support plugins
2018-10-25 16:19:22 +02:00
Benedikt Tutzer
e7880bab20
removed debug output from make
2018-10-25 15:06:55 +02:00
Benedikt Tutzer
a13cba31c9
removed deletes
2018-10-25 15:06:26 +02:00
Benedikt Tutzer
05a9adfdeb
added py_wrap_generator
2018-10-25 12:27:56 +02:00
Benedikt Tutzer
6f8abc1143
Exposed generator script to make-process
2018-09-19 10:32:34 +02:00
Benedikt Tutzer
604734b484
added functions whose definitions are split over multiple lines
2018-08-23 14:48:20 +02:00
Benedikt Tutzer
586d7df7e2
added default yosys license text
2018-08-23 14:39:44 +02:00
Benedikt Tutzer
ba18e0f81a
Fixed segfault / multiple free issue with lists
2018-08-23 13:57:37 +02:00
Benedikt Tutzer
0ecfffa69c
Do not pass heap object to Python. This way they should be completely managed by Python and destroyed when out of scope. Also, the file in which a function/struct was found is added to the comment before the function
2018-08-22 14:42:42 +02:00
Benedikt Tutzer
60608a86bb
Fixed Identation
2018-08-22 11:59:22 +02:00
Benedikt Tutzer
038caab4e0
Wrapped functions that use unsigned int or type_t as types
2018-08-21 15:25:43 +02:00
Benedikt Tutzer
4acb29db0c
added operators <, == and !=
2018-08-21 14:49:35 +02:00
Benedikt Tutzer
334bfce4c4
Added previousely missed functions
2018-08-21 13:15:08 +02:00
Benedikt Tutzer
29efc9d0b1
Deleted duplicate Destructor
2018-08-21 11:07:59 +02:00
Benedikt Tutzer
95d65971f3
added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile
2018-08-20 16:04:43 +02:00
Benedikt Tutzer
d87c7df27f
Two passes are not allowed to have the same filename
2018-08-20 15:28:09 +02:00
Benedikt Tutzer
d41c68ee5a
The share directory cannot be searched when used as a Python library, only in shell mode
2018-08-20 15:27:50 +02:00
Benedikt Tutzer
6d18837d62
Python passes are now looked for in share/plugins and can be added by specifying a relative or absolute path
2018-08-20 15:11:06 +02:00
Benedikt Tutzer
5864db3c2b
Fixed issue when using a python plugin in the yosys shell
2018-08-20 14:44:03 +02:00
Benedikt Tutzer
d79a2808cf
Python Passes can now be added with the -m option or with the plugin command. There are still issues when run in shell mode, but they can be used just fine in a python script
2018-08-16 16:00:11 +02:00
Benedikt Tutzer
bf7b73acfc
Added Wrappers for:
...
-IdString
-Const
-CaseRule
-SwitchRule
-SyncRule
-Process
-SigChunk
-SigBit
-SigSpec
With all their member functions as well as the remaining member
functions for Cell, Wire, Module and Design and static functions of
rtlil.h
2018-08-13 15:18:46 +02:00
Benedikt Tutzer
416946a16a
Saving id and pointer to c++ object. Object is valid only if both id and pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more
2018-08-01 10:57:57 +02:00
Benedikt Tutzer
79d7e608cf
Setup is called automatically when the module is loaded, shutdown when python exits
2018-08-01 10:57:46 +02:00
Benedikt Tutzer
57d2197703
Cleaned up comments
2018-08-01 10:57:41 +02:00
Benedikt Tutzer
b57dafce68
removed unused library and already present compiler flag
2018-08-01 10:57:33 +02:00
Benedikt Tutzer
0371519c39
Added Monitor class that can monitor all changes in a Design or in a Module
2018-07-10 12:51:02 +02:00
Benedikt Tutzer
e7d3f3cd46
added destructors for wires and cells
2018-07-10 08:52:36 +02:00
Benedikt Tutzer
55df7fff19
removed debug output
2018-07-09 16:02:10 +02:00
Benedikt Tutzer
da8083dbd0
commands can now be run on arbitrary designs, not only on the active one
2018-07-09 16:01:56 +02:00
Benedikt Tutzer
8ebaeecd83
multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues
2018-07-09 15:48:06 +02:00
Benedikt Tutzer
7911379d4a
Introduced namespace and removed class-prefixes to increase readability
2018-06-28 15:07:21 +02:00
Benedikt Tutzer
ccb4dcd013
changed references from hash-ids to IdString names
2018-06-28 14:44:28 +02:00
Benedikt Tutzer
a27fa1833e
added wrappers for Design, Modules, Cells and Wires
2018-06-25 17:08:29 +02:00
Benedikt Tutzer
4d4117c998
added ENABLE_PYTHON option in build environment
2018-06-22 11:15:03 +02:00
Clifford Wolf
d412b17259
Add simplified "read" command, enable extnets in implicit Verific import
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-21 16:56:55 +02:00
Clifford Wolf
9e096b1512
Merge branch 'master' of github.com:YosysHQ/yosys
2018-06-20 23:45:26 +02:00
Clifford Wolf
5f2bc1ce76
Add automatic verific import in hierarchy command
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-20 23:45:01 +02:00
Clifford Wolf
c1d6934663
Merge pull request #572 from q3k/q3k/fix-protobuf-build
...
Fix protobuf build
2018-06-20 20:40:59 +02:00
Sergiusz Bazanski
1690dafde1
Fix protobuf build
2018-06-20 19:28:43 +01:00
Clifford Wolf
626b555244
Merge pull request #571 from q3k/q3k/protobuf-backend
...
Add Protobuf backend
2018-06-19 15:02:04 +02:00
Serge Bazanski
53e9a1549c
Add Protobuf backend
...
Signed-off-by: Serge Bazanski <q3k@symbioticeda.com>
2018-06-19 13:34:56 +01:00
Clifford Wolf
675a44b41a
Be slightly less aggressive in "deminout" pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-19 14:29:38 +02:00
Clifford Wolf
25c5002f83
Merge pull request #570 from edcote/patch-4
...
Include module name for area summary stats
2018-06-19 13:47:39 +02:00
Edmond Cote
d89560a0ba
Include module name for area summary stats
...
The PR prints the name of the module when displaying the final area count.
Pros:
- Easier for the user to `grep` for area information about a specific module
Cons:
- Arguably more verbose, less "pretty" than author desires
Verification:
~~~~
30c30
< Chip area for this module: 20616.349000
---
> Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000
70c70
< Chip area for this module: 88.697700
---
> Chip area for module '\picorv32_axi_adapter': 88.697700
102c102
< Chip area for this module: 20705.046700
---
> Chip area for top module '\picorv32_axi': 20705.046700
~~~~
2018-06-18 17:29:01 -07:00
Clifford Wolf
0ff0ce4973
Bugfix in liberty parser (as suggested by aiju in #569 )
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-15 18:56:44 +02:00
Clifford Wolf
57fc8dd582
Add "synth_ice40 -json"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-13 13:35:10 +02:00
Clifford Wolf
83631555dd
Fix ice40_opt for cases where a port is connected to a signal with width != 1
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-11 18:12:42 +02:00