Clifford Wolf
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67b0ce2578
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Only generate write-enable $and if WE is not constant 1 in memory_map
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2014-02-02 21:27:26 +01:00 |
Clifford Wolf
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83fa652820
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Added constant-clock case to opt_rmdff
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2014-02-02 21:09:08 +01:00 |
Clifford Wolf
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6983d3f10b
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presentation progress
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2014-02-02 17:57:14 +01:00 |
Clifford Wolf
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aa732b0c73
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Added show -notitle option
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2014-02-02 17:55:32 +01:00 |
Clifford Wolf
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9808acdc75
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Added delete command
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2014-02-02 17:11:19 +01:00 |
Clifford Wolf
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a9e2d86f86
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Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax
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2014-02-02 16:47:17 +01:00 |
Clifford Wolf
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0f88e28693
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presentation progress
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2014-02-02 13:30:49 +01:00 |
Clifford Wolf
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9334c34170
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presentation progress
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2014-02-02 13:06:28 +01:00 |
Clifford Wolf
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cdd6e11af5
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Added support for blanks after -I and -D in read_verilog
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2014-02-02 13:06:21 +01:00 |
Clifford Wolf
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f4f0bd6eef
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Fixed a bug in miter command
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2014-02-01 22:53:27 +01:00 |
Clifford Wolf
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374674aff4
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Added sat -show-inputs and -show-outputs
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2014-02-01 22:52:44 +01:00 |
Clifford Wolf
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caf540d1ad
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Added show -color support for cells and finished show -label implementation
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2014-02-01 18:23:32 +01:00 |
Clifford Wolf
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af325bf206
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Fixed comment/eol parsing in ilang frontend
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2014-02-01 17:28:02 +01:00 |
Clifford Wolf
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d06258f74f
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Added constant size expression support of sized constants
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2014-02-01 13:50:23 +01:00 |
Clifford Wolf
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1e2440e7ed
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Added note about SystemVerilog assert statement to README
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2014-02-01 13:04:49 +01:00 |
Clifford Wolf
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fa92722358
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Added miter command
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2014-02-01 10:35:56 +01:00 |
Clifford Wolf
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1c8f6f21b4
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Progress on presentation
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2014-01-31 12:48:31 +01:00 |
Clifford Wolf
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ed8ad99960
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More changes to techlibs/common/simlib.v for LEC
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2014-01-31 11:21:29 +01:00 |
Clifford Wolf
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36a808c572
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presentation progress
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2014-01-30 15:25:09 +01:00 |
Clifford Wolf
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4df7e03ec9
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Bugfix in name resolution with generate blocks
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2014-01-30 15:01:28 +01:00 |
Clifford Wolf
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672229eda5
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Added yosys -H for command list
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2014-01-30 12:32:59 +01:00 |
Clifford Wolf
|
34b39ec28a
|
presentation progress
|
2014-01-29 15:56:58 +01:00 |
Clifford Wolf
|
cbe77bf844
|
presentation progress
|
2014-01-29 12:15:38 +01:00 |
Clifford Wolf
|
aceab5fc08
|
Tiny change in example script in README
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2014-01-29 11:11:10 +01:00 |
Clifford Wolf
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96084e9864
|
Added -h command line option
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2014-01-29 11:10:39 +01:00 |
Clifford Wolf
|
6a7d7e847d
|
Added test comments to techlibs/cmos/cmos_cells.lib
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2014-01-29 10:51:02 +01:00 |
Clifford Wolf
|
c46b23ab23
|
Updated ABC to hg rev e6b09e1
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2014-01-29 10:50:15 +01:00 |
Clifford Wolf
|
375c4dddc1
|
Added read_verilog -icells option
|
2014-01-29 00:59:28 +01:00 |
Clifford Wolf
|
a86f33653d
|
Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)
|
2014-01-29 00:36:03 +01:00 |
Clifford Wolf
|
961b791272
|
presentation progress
|
2014-01-28 20:28:22 +01:00 |
Clifford Wolf
|
2cb47355d4
|
Renamed manual/FILES_* directories
|
2014-01-28 06:55:47 +01:00 |
Clifford Wolf
|
842ca2f011
|
Progress on presentation
|
2014-01-28 06:51:50 +01:00 |
Clifford Wolf
|
a3ac6b6f47
|
Progress on presentation
|
2014-01-27 20:42:35 +01:00 |
Clifford Wolf
|
fb4c3dff33
|
Added first presentation slides
|
2014-01-27 17:08:19 +01:00 |
Clifford Wolf
|
fa103e55ad
|
Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys
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2014-01-26 02:29:19 +01:00 |
Clifford Wolf
|
fd6ca84f3c
|
Merge pull request #21 from hansiglaser/master
beautified write_intersynth, enabled multiple "-map" for the extract pass
|
2014-01-25 17:28:17 -08:00 |
Johann Glaser
|
e9a2094774
|
enabled multiple "-map" for the extract pass
|
2014-01-25 21:11:34 +01:00 |
Johann Glaser
|
f13b3518aa
|
beautified write_intersynth
|
2014-01-25 20:16:38 +01:00 |
Ahmed Irfan
|
0325efe172
|
root bug corrected
|
2014-01-25 19:33:24 +01:00 |
Clifford Wolf
|
c1ed2607fb
|
Added support for // comments in liberty parser
|
2014-01-25 06:32:16 +01:00 |
Clifford Wolf
|
a139b49401
|
Merge branch 'btor'
|
2014-01-24 23:44:46 +01:00 |
Ahmed Irfan
|
137742786e
|
removed regex include
|
2014-01-24 18:04:37 +01:00 |
Ahmed Irfan
|
2e44b1b73a
|
merged clifford changes + removed regex
|
2014-01-24 17:35:42 +01:00 |
Clifford Wolf
|
210dda286f
|
Use techmap -share_map in btor scripts
|
2014-01-24 15:52:16 +01:00 |
Clifford Wolf
|
6804edd5d4
|
Moved btor scripts to backends/btor/
|
2014-01-24 15:48:07 +01:00 |
Clifford Wolf
|
da26bb4378
|
Restored Makefile
|
2014-01-24 15:47:09 +01:00 |
Clifford Wolf
|
ec167350b4
|
Restored IdString::check()
|
2014-01-24 15:46:41 +01:00 |
Clifford Wolf
|
d8300d1fb8
|
Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor
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2014-01-24 15:43:42 +01:00 |
Clifford Wolf
|
0b47d907d3
|
Fixed handling of unsized constants in verilog frontend
|
2014-01-24 15:05:24 +01:00 |
Ahmed Irfan
|
761b8f99d7
|
minor change in script
|
2014-01-24 15:00:43 +01:00 |