Eddie Hung
da5f830395
Merge pull request #1098 from YosysHQ/xaig
...
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
2019-06-28 10:59:03 -07:00
Eddie Hung
fb30fcb7c5
Undo iterator based Module::remove() for cells, as containers will not
...
invalidate
2019-06-27 15:03:21 -07:00
Bogdan Vukobratovic
0f32cb4e0a
Merge remote-tracking branch 'upstream/master'
2019-06-27 12:11:47 +02:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Ben Widawsky
8767ec3fbd
Add a few more filename rewrites
...
This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"
Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-20 10:27:59 -07:00
Clifford Wolf
73bd1d59a7
Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046
2019-06-20 13:04:04 +02:00
Clifford Wolf
b3441935b1
Merge pull request #1100 from bwidawsk/home
...
Support ~ in filename parsing
2019-06-19 10:52:59 +02:00
whitequark
df6576edc8
In RTLIL::Module::check(), check process invariants.
2019-06-19 05:22:13 +00:00
Ben Widawsky
468c41d997
Support ~ for home directory
...
This is tested on Linux only
v2:
Wrap functioanlity in ifndef _WIN32 (eddiehung)
Find '~/' instead of '~' (cliffordwolf)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-18 14:38:40 -07:00
Eddie Hung
b45d06d7a3
Fix leak removing cells during ABC integration; also preserve attr
2019-06-17 12:54:24 -07:00
Eddie Hung
a48b5bfaa5
Further cleanup based on @daveshah1
2019-06-14 12:25:06 -07:00
Bogdan Vukobratovic
8451cbea89
Move netlist helper module to passes/opt for the time being
2019-06-14 12:14:02 +02:00
Bogdan Vukobratovic
fe651922cb
Merge remote-tracking branch 'upstream/master'
2019-06-14 12:06:57 +02:00
Bogdan Vukobratovic
53695e6729
Prepare for situation when port of the signal cannot be found
2019-06-14 11:39:24 +02:00
Eddie Hung
d09d4e0706
Move ConstEvalAig to aigerparse.cc
2019-06-13 16:28:11 -07:00
Eddie Hung
63e2f83632
More slimming
2019-06-13 13:29:03 -07:00
Eddie Hung
d39a5a77a9
Add ConstEvalAig specialised for AIGs
2019-06-13 13:13:48 -07:00
Bogdan Vukobratovic
8665f48879
Implement disconnection of constant register bits
2019-06-13 19:35:37 +02:00
Bogdan Vukobratovic
4912567cbf
Pass SigBit by value to Netlist algorithms
2019-06-13 15:42:45 +02:00
Bogdan Vukobratovic
d69989b8d2
Rename satgen_algo.h -> algo.h, code cleanup and refactoring
2019-06-12 19:35:05 +02:00
Eddie Hung
f7a9769c14
Merge remote-tracking branch 'origin/master' into xaig
2019-06-12 08:50:39 -07:00
Bogdan Vukobratovic
9892df17ef
Generate satgen instance instead of calling sat pass
2019-06-11 11:47:13 +02:00
Bogdan Vukobratovic
d097f423d1
Refactor driver map generation
...
- Implement iterators over the driver map that enumerate signals and cells
within the cones of the signal
2019-06-10 21:42:35 +02:00
Clifford Wolf
211d85cfcc
Fixes and cleanups in AST_TECALL handling
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 12:41:09 +02:00
Clifford Wolf
a3bbc5365b
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
2019-06-07 12:08:42 +02:00
Clifford Wolf
ba2185ead8
Refactor hierarchy wand/wor handling
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 16:43:25 +02:00
Clifford Wolf
0971f772d7
Fix handling of warning and error messages within log_make_debug-blocks
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-22 13:46:38 +02:00
Clifford Wolf
287de4b848
Add rewrite_sigspecs2, Improve remove() wires
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 16:01:00 +02:00
Clifford Wolf
3870e7cf29
Merge pull request #991 from kristofferkoch/gcc9-warnings
...
Fix all warnings that occurred when compiling with gcc9
2019-05-08 11:25:22 +02:00
Kristoffer Ellersgaard Koch
30c762d3a1
Fix all warnings that occurred when compiling with gcc9
2019-05-08 10:27:14 +02:00
Clifford Wolf
c582a25bdb
Merge pull request #998 from mdaiter/get_bool_attribute_opts
...
Minor optimization to get_attribute_bool
2019-05-08 08:34:35 +02:00
Matthew Daiter
6e629d2895
Minor optimization to get_attribute_bool
2019-05-07 22:04:28 -05:00
Matthew Daiter
bafbb9ee90
Optimize ceil_log2 function
2019-05-07 12:17:56 -05:00
Clifford Wolf
87426f5a06
Improve write_verilog specify support
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 08:46:24 +02:00
Eddie Hung
d9c4644e88
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
Udi Finkelstein
ac10e7d96d
Initial implementation of elaboration system tasks
...
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
2019-05-03 03:10:43 +03:00
Clifford Wolf
9268cd1613
Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:19:10 +02:00
Oleg Endo
4f15e7f00f
fix codestyle formatting
2019-04-29 19:20:33 +09:00
Oleg Endo
e531fb203a
escape spaces with backslash when writing dep file
...
filenames are sparated by spaces in the dep file. if a filename in the
dep file contains spaces they must be escaped, otherwise the tool that
reads the dep file will see multiple wrong filenames.
2019-04-29 16:13:34 +09:00
Clifford Wolf
64925b4e8f
Improve $specrule interface
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:57:10 +02:00
Clifford Wolf
4575e4ad86
Improve $specrule interface
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:18:04 +02:00
Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
aec2475a9d
Add CellTypes support for $specify2 and $specify3
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e1d73e03d3
Add InternalCellChecker support for $specify2 and $specify3
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
3cc95fb4be
Add specify parser
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
David Shah
742c2f245d
Fixes for OAI4 cell implementation
...
Fixes #955 and the underlying issue in #954
Signed-off-by: David Shah <dave@ds0.me>
2019-04-23 17:54:00 +01:00
Eddie Hung
2c6358ea25
Remove kernel/cost.cc since master has refactored it
2019-04-22 11:21:17 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Clifford Wolf
e158ea2097
Add log_debug() framework
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 17:25:52 +02:00
Clifford Wolf
99d5435650
Merge pull request #905 from christian-krieg/feature/python_bindings
...
Feature/python bindings
2019-04-22 14:47:52 +02:00
Eddie Hung
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
Clifford Wolf
5b915f0153
Add "wbflip" command
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 11:04:46 +02:00
Eddie Hung
290a798cec
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:32:00 -07:00
Eddie Hung
c997a77014
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:19:45 -07:00
Eddie Hung
8fe0a961b3
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
2019-04-18 09:00:06 -07:00
Clifford Wolf
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Clifford Wolf
dfb242c905
Add "read_ilang -lib"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-05 17:31:49 +02:00
Benedikt Tutzer
827a96d3a3
Global lists in rtlil.cc are now static objects
2019-04-03 14:27:39 +02:00
Benedikt Tutzer
0774a500d4
Added support for changing Yosys namespace
2019-04-03 12:21:21 +02:00
Benedikt Tutzer
072c939380
Fixed identation
2019-04-01 13:36:01 +02:00
Benedikt Tutzer
03d1606b42
Merge remote-tracking branch 'origin/master' into feature/python_bindings
2019-03-28 12:16:39 +01:00
Clifford Wolf
3b796c033c
Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 14:38:48 +01:00
Clifford Wolf
370db33a4c
Add fmcombine pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-15 20:46:17 +01:00
Clifford Wolf
76c9c350e7
Add hashlib "<container>::element(int n)" methods
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
Clifford Wolf
1cd04a6838
Fix a bug in handling quotes in multi-cmd lines in Yosys scripts
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 21:15:11 +01:00
Clifford Wolf
20c6a8c9b0
Improve determinism of IdString DB for similar scripts
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-11 20:12:28 +01:00
Clifford Wolf
d9bb5f3637
Add ENABLE_GLOB Makefile switch
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-11 01:08:36 -07:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Eddie Hung
3ea0161ae7
Add IdString::ends_with()
2019-02-26 12:04:16 -08:00
Clifford Wolf
c521f4632f
Merge pull request #819 from YosysHQ/clifford/optd
...
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
2019-02-22 06:55:48 +01:00
Eddie Hung
a8803a1519
Merge remote-tracking branch 'origin/master' into xaig
2019-02-21 11:23:00 -08:00
Clifford Wolf
0a6588569b
Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 15:51:59 +01:00
Clifford Wolf
953e0bf88d
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 14:27:46 +01:00
Clifford Wolf
246391200e
Add FF support to wreduce
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:36:42 +01:00
Eddie Hung
edf7267019
Refactor kernel/cost.h definition into cost.cc
2019-02-08 13:58:20 -08:00
Clifford Wolf
e70ebe557c
Add optional nullstr argument to log_id()
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:06:48 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
18291c20d2
proc_clean: remove any empty cases if all cases use all-def compare.
2018-12-23 09:04:30 +00:00
whitequark
2ca237e086
tcl: add support for passing arguments to scripts.
2018-12-20 07:32:24 +00:00
Clifford Wolf
e90195b737
Improve ConstEval error handling for non-eval cell types
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-29 05:07:40 +01:00
Jon Burgess
6732e56632
Avoid assert when label is an empty string
...
Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:
$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
...
/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed.
802 if (label.back() == ':' && GetSize(label) > 1)
(gdb) p label
$1 = ""
2018-10-28 14:57:04 +00:00
whentze
9ed77f5ba8
fix unhandled std::out_of_range when calling yosys with 3-character argument
2018-10-22 19:40:22 +02:00
Ruben Undheim
c50afc4246
Documentation improvements etc.
...
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
...
This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Adrian Wheeldon
1355492c89
Fix IdString M in setup_stdcells()
2018-10-04 15:36:26 +01:00
Benedikt Tutzer
6f8abc1143
Exposed generator script to make-process
2018-09-19 10:32:34 +02:00
Miodrag Milanovic
c5e9034834
Fix Cygwin build and document needed packages
2018-09-19 10:16:53 +02:00
Benedikt Tutzer
604734b484
added functions whose definitions are split over multiple lines
2018-08-23 14:48:20 +02:00
Benedikt Tutzer
586d7df7e2
added default yosys license text
2018-08-23 14:39:44 +02:00
Benedikt Tutzer
ba18e0f81a
Fixed segfault / multiple free issue with lists
2018-08-23 13:57:37 +02:00
Benedikt Tutzer
0ecfffa69c
Do not pass heap object to Python. This way they should be completely managed by Python and destroyed when out of scope. Also, the file in which a function/struct was found is added to the comment before the function
2018-08-22 14:42:42 +02:00
Benedikt Tutzer
60608a86bb
Fixed Identation
2018-08-22 11:59:22 +02:00
Benedikt Tutzer
038caab4e0
Wrapped functions that use unsigned int or type_t as types
2018-08-21 15:25:43 +02:00
Benedikt Tutzer
4acb29db0c
added operators <, == and !=
2018-08-21 14:49:35 +02:00
Benedikt Tutzer
334bfce4c4
Added previousely missed functions
2018-08-21 13:15:08 +02:00
Benedikt Tutzer
29efc9d0b1
Deleted duplicate Destructor
2018-08-21 11:07:59 +02:00