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9069 Commits

Author SHA1 Message Date
Eddie Hung 7d86aceee3 Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy 2020-02-27 10:17:29 -08:00
Eddie Hung 3728ef1765 ice40: fix specify for inverted clocks 2020-02-27 10:17:29 -08:00
Eddie Hung aac309626b Fix tests by gating some specify constructs from iverilog 2020-02-27 10:17:29 -08:00
Eddie Hung 977262c803 Update simple_abc9 tests 2020-02-27 10:17:29 -08:00
Eddie Hung e22fee6cdd abc9_ops: ignore (* abc9_flop *) if not '-dff' 2020-02-27 10:17:29 -08:00
Eddie Hung a76520112d ice40: specify fixes 2020-02-27 10:17:29 -08:00
Eddie Hung 7c92b6852f abc9_ops: sort LUT delays to be ascending 2020-02-27 10:17:29 -08:00
Eddie Hung fb60d82971 ice40: move over to specify blocks for -abc9 2020-02-27 10:17:29 -08:00
Eddie Hung a85c55113f synth_ecp5: use +/abc9_model.v 2020-02-27 10:17:29 -08:00
Eddie Hung 8408c13405 Update xilinx for ABC9 2020-02-27 10:17:29 -08:00
Eddie Hung ac24a23e31 Create +/abc9_model.v for $__ABC9_{DELAY,FF_} 2020-02-27 10:17:29 -08:00
Eddie Hung 7317521c6f abc9_ops: output LUT area 2020-02-27 10:17:29 -08:00
Eddie Hung d2284715fa ecp5: remove small LUT entries 2020-02-27 10:17:29 -08:00
Eddie Hung 0ed550d83c abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTs 2020-02-27 10:17:29 -08:00
Eddie Hung ccc84f8923 Fix commented out specify statement 2020-02-27 10:17:29 -08:00
Eddie Hung 12d70ca8fb xilinx: improve specify functionality 2020-02-27 10:17:29 -08:00
Eddie Hung 46a89d7264 ecp5: deprecate abc9_{arrival,required} and *.{lut,box} 2020-02-27 10:17:29 -08:00
Eddie Hung 577545488a xilinx: use specify blocks in place of abc9_{arrival,required} 2020-02-27 10:17:29 -08:00
Eddie Hung 0e7c55e2a7 Auto-generate .box/.lut files from specify blocks 2020-02-27 10:17:29 -08:00
Eddie Hung 3d6603792d abc9_ops: assert on $specify2 properties 2020-02-27 10:17:29 -08:00
Eddie Hung 74f49b1f55 abc9_ops: -prep_box, to be called once 2020-02-27 10:17:29 -08:00
Eddie Hung 5643c1b8c5 abc9_ops: -prep_lut and -write_lut to auto-generate LUT library 2020-02-27 10:17:29 -08:00
Claire Wolf ab8826ae36
Merge pull request #1709 from rqou/coolrunner2_counter 
Improve CoolRunner-II optimization by using extract_counter pass
 2020-02-27 19:05:56 +01:00
Claire Wolf 47228feb77
Merge pull request #1708 from rqou/coolrunner2-buf-fix 
coolrunner2: Separate and improve buffer cell insertion pass
 2020-02-27 19:03:59 +01:00
Piotr Binkowski 62ab100c61 xilinx: mark IOBUFDSE3 IOB pin as external 2020-02-27 13:15:57 +01:00
Miodrag Milanović 036c46de1e
Merge pull request #1705 from YosysHQ/logger_pass 
Logger pass
 2020-02-26 13:32:49 +01:00
Miodrag Milanovic 80656ad178 Remove tests for now 2020-02-26 09:49:41 +01:00
Alberto Gonzalez f80fe8dc22
Change attribute search value to specify precise location instead of simple line number. 2020-02-24 02:41:08 +00:00
Alberto Gonzalez 2c2f092c90
Change attribute search value to specify precise location instead of simple line number. 2020-02-24 01:39:36 +00:00
Miodrag Milanovic c1cee15d64 Add tests for logger pass 2020-02-23 10:56:39 +01:00
Miodrag Milanovic 1c569fe06a Remove duplicate warning detection 2020-02-23 10:56:27 +01:00
Miodrag Milanovic 48eed2860c Fix line endings 2020-02-23 10:05:21 +01:00
Alberto Gonzalez f0afd65035
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
Eddie Hung 6edca05793
Merge pull request #1715 from boqwxp/master 
Closes #1714. Fix make failure when NDEBUG=1.
 2020-02-22 11:29:22 -08:00
Marcus Comstedt 48a9b4f616 ecp5: Add missing parameter to \$__ECP5_PDPW16KD 2020-02-22 15:51:25 +01:00
Miodrag Milanovic 010d651450 Update explanation for expect-no-warnings 2020-02-22 10:53:23 +01:00
Miodrag Milanovic d079ab9d19 Handle expect no warnings together with expected 2020-02-22 10:52:46 +01:00
Miodrag Milanovic 596bb2d443 Check other regex parameters 2020-02-22 10:31:56 +01:00
Alberto Gonzalez 750e7a9a54
Closes #1714. Fix make failure when NDEBUG=1. 2020-02-22 06:29:11 +00:00
Eddie Hung 760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve 
Improve specify parser
 2020-02-21 09:15:17 -08:00
Claire Wolf cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum 
Enum support
 2020-02-20 18:17:25 +01:00
Miodrag Milanovic 419e67c170 check for regex errors 2020-02-20 11:41:37 +01:00
Eddie Hung ea4bd161b6 verilog: add support for more delays than just rise/fall 2020-02-19 11:09:37 -08:00
Eddie Hung 1d401a7991 clean: ignore specify-s inside cells when determining whether to keep 2020-02-19 10:45:10 -08:00
Miodrag Milanovic 70db8e9200 Prevent double error message 2020-02-17 16:46:34 +01:00
Miodrag Milanovic 5641b0248f Option to expect no warnings 2020-02-17 15:36:06 +01:00
Miodrag Milanovic d8735b2913 Add to changelog 2020-02-17 15:08:35 +01:00
Miodrag Milanovic be977cf7eb No new error if already failing 2020-02-17 12:54:36 +01:00
R. Ou 13d0ff4a5f coolrunner2: Use extract_counter to optimize counters 
This tends to make much more efficient pterm usage compared to just
throwing the problem at ABC
 2020-02-17 03:09:40 -08:00
R. Ou fec7dc5c9e extract_counter: Implement extracting up counters 2020-02-17 03:08:52 -08:00