mirror of https://github.com/YosysHQ/yosys.git
Add tests for logger pass
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logger -werror "is implicitly declared." -expect error "is implicitly declared." 1
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read_verilog << EOF
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module top(...);
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assign b = w;
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endmodule
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EOF
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logger -expect-no-warnings -nowarn "is implicitly declared."
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read_verilog << EOF
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module top(...);
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assign b = w;
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endmodule
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EOF
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logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1
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read_verilog << EOF
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module top(...);
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assign b = w;
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endmodule
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EOF
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@ -0,0 +1,6 @@
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logger -expect warning "is implicitly declared." 2
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read_verilog << EOF
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module top(...);
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assign b = w;
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endmodule
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EOF
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