Add tests for logger pass

This commit is contained in:
Miodrag Milanovic 2020-02-23 10:56:39 +01:00
parent 1c569fe06a
commit c1cee15d64
4 changed files with 24 additions and 0 deletions

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logger -werror "is implicitly declared." -expect error "is implicitly declared." 1
read_verilog << EOF
module top(...);
assign b = w;
endmodule
EOF

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logger -expect-no-warnings -nowarn "is implicitly declared."
read_verilog << EOF
module top(...);
assign b = w;
endmodule
EOF

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logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1
read_verilog << EOF
module top(...);
assign b = w;
endmodule
EOF

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logger -expect warning "is implicitly declared." 2
read_verilog << EOF
module top(...);
assign b = w;
endmodule
EOF