Remove tests for now

tests/various/logger_error.ys

@@ -1,6 +0,0 @@
-logger -werror "is implicitly declared." -expect error "is implicitly declared." 1
-read_verilog << EOF
-module top(...);
-	assign b = w;
-endmodule
-EOF

tests/various/logger_nowarning.ys

@@ -1,6 +0,0 @@
-logger -expect-no-warnings -nowarn "is implicitly declared."
-read_verilog << EOF
-module top(...);
-	assign b = w;
-endmodule
-EOF

tests/various/logger_warn.ys

@@ -1,6 +0,0 @@
-logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1
-read_verilog << EOF
-module top(...);
-	assign b = w;
-endmodule
-EOF

tests/various/logger_warning.ys

@@ -1,6 +0,0 @@
-logger -expect warning "is implicitly declared." 2
-read_verilog << EOF
-module top(...);
-	assign b = w;
-endmodule
-EOF