Eddie Hung
3ea0161ae7
Add IdString::ends_with()
2019-02-26 12:04:16 -08:00
Clifford Wolf
c521f4632f
Merge pull request #819 from YosysHQ/clifford/optd
...
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
2019-02-22 06:55:48 +01:00
Eddie Hung
a8803a1519
Merge remote-tracking branch 'origin/master' into xaig
2019-02-21 11:23:00 -08:00
Clifford Wolf
0a6588569b
Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 15:51:59 +01:00
Clifford Wolf
953e0bf88d
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 14:27:46 +01:00
Clifford Wolf
246391200e
Add FF support to wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:36:42 +01:00
Eddie Hung
edf7267019
Refactor kernel/cost.h definition into cost.cc
2019-02-08 13:58:20 -08:00
Clifford Wolf
e70ebe557c
Add optional nullstr argument to log_id()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:06:48 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
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The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
18291c20d2
proc_clean: remove any empty cases if all cases use all-def compare.
2018-12-23 09:04:30 +00:00
whitequark
2ca237e086
tcl: add support for passing arguments to scripts.
2018-12-20 07:32:24 +00:00
Clifford Wolf
e90195b737
Improve ConstEval error handling for non-eval cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-29 05:07:40 +01:00
Jon Burgess
6732e56632
Avoid assert when label is an empty string
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Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:
$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
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/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed.
802 if (label.back() == ':' && GetSize(label) > 1)
(gdb) p label
$1 = ""
2018-10-28 14:57:04 +00:00
whentze
9ed77f5ba8
fix unhandled std::out_of_range when calling yosys with 3-character argument
2018-10-22 19:40:22 +02:00
Ruben Undheim
c50afc4246
Documentation improvements etc.
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- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Adrian Wheeldon
1355492c89
Fix IdString M in setup_stdcells()
2018-10-04 15:36:26 +01:00
Benedikt Tutzer
6f8abc1143
Exposed generator script to make-process
2018-09-19 10:32:34 +02:00
Miodrag Milanovic
c5e9034834
Fix Cygwin build and document needed packages
2018-09-19 10:16:53 +02:00
Benedikt Tutzer
604734b484
added functions whose definitions are split over multiple lines
2018-08-23 14:48:20 +02:00
Benedikt Tutzer
586d7df7e2
added default yosys license text
2018-08-23 14:39:44 +02:00
Benedikt Tutzer
ba18e0f81a
Fixed segfault / multiple free issue with lists
2018-08-23 13:57:37 +02:00
Benedikt Tutzer
0ecfffa69c
Do not pass heap object to Python. This way they should be completely managed by Python and destroyed when out of scope. Also, the file in which a function/struct was found is added to the comment before the function
2018-08-22 14:42:42 +02:00
Benedikt Tutzer
60608a86bb
Fixed Identation
2018-08-22 11:59:22 +02:00
Benedikt Tutzer
038caab4e0
Wrapped functions that use unsigned int or type_t as types
2018-08-21 15:25:43 +02:00
Benedikt Tutzer
4acb29db0c
added operators <, == and !=
2018-08-21 14:49:35 +02:00
Benedikt Tutzer
334bfce4c4
Added previousely missed functions
2018-08-21 13:15:08 +02:00
Benedikt Tutzer
29efc9d0b1
Deleted duplicate Destructor
2018-08-21 11:07:59 +02:00
Benedikt Tutzer
95d65971f3
added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile
2018-08-20 16:04:43 +02:00
Benedikt Tutzer
d41c68ee5a
The share directory cannot be searched when used as a Python library, only in shell mode
2018-08-20 15:27:50 +02:00
Benedikt Tutzer
6d18837d62
Python passes are now looked for in share/plugins and can be added by specifying a relative or absolute path
2018-08-20 15:11:06 +02:00
Benedikt Tutzer
5864db3c2b
Fixed issue when using a python plugin in the yosys shell
2018-08-20 14:44:03 +02:00
Benedikt Tutzer
d79a2808cf
Python Passes can now be added with the -m option or with the plugin command. There are still issues when run in shell mode, but they can be used just fine in a python script
2018-08-16 16:00:11 +02:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override
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Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
litghost
80d7e007ff
Map .eblif extension as blif.
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Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
2018-08-13 14:02:53 -07:00
Benedikt Tutzer
bf7b73acfc
Added Wrappers for:
...
-IdString
-Const
-CaseRule
-SwitchRule
-SyncRule
-Process
-SigChunk
-SigBit
-SigSpec
With all their member functions as well as the remaining member
functions for Cell, Wire, Module and Design and static functions of
rtlil.h
2018-08-13 15:18:46 +02:00
Benedikt Tutzer
416946a16a
Saving id and pointer to c++ object. Object is valid only if both id and pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more
2018-08-01 10:57:57 +02:00
Benedikt Tutzer
79d7e608cf
Setup is called automatically when the module is loaded, shutdown when python exits
2018-08-01 10:57:46 +02:00
Benedikt Tutzer
57d2197703
Cleaned up comments
2018-08-01 10:57:41 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Henner Zeller
1a60126a34
Provide source-location logging.
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o Provide log_file_warning() and log_file_error() that prefix the log
message with <filename>:<lineno>: to be easily picked up by IDEs that
need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
2018-07-19 10:22:02 -07:00
Benedikt Tutzer
0371519c39
Added Monitor class that can monitor all changes in a Design or in a Module
2018-07-10 12:51:02 +02:00
Benedikt Tutzer
e7d3f3cd46
added destructors for wires and cells
2018-07-10 08:52:36 +02:00
Benedikt Tutzer
55df7fff19
removed debug output
2018-07-09 16:02:10 +02:00
Benedikt Tutzer
da8083dbd0
commands can now be run on arbitrary designs, not only on the active one
2018-07-09 16:01:56 +02:00
Benedikt Tutzer
8ebaeecd83
multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues
2018-07-09 15:48:06 +02:00
Benedikt Tutzer
7911379d4a
Introduced namespace and removed class-prefixes to increase readability
2018-06-28 15:07:21 +02:00
Benedikt Tutzer
ccb4dcd013
changed references from hash-ids to IdString names
2018-06-28 14:44:28 +02:00
Benedikt Tutzer
a27fa1833e
added wrappers for Design, Modules, Cells and Wires
2018-06-25 17:08:29 +02:00
Robert Ou
0abe7c6c77
Modify emscripten main to mount nodefs and to run arg as a script
2018-05-18 22:53:52 -07:00
Robert Ou
bd87462b47
Fix reading techlibs under emscripten
2018-05-18 22:42:33 -07:00
Christian Krämer
c1ecb1b2f1
Add "#ifdef __FreeBSD__"
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(Re-commit e3575a8
with corrected author field)
2018-05-13 13:08:26 +02:00
Clifford Wolf
1167538d26
Revert "Add "#ifdef __FreeBSD__""
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This reverts commit e3575a86c5
.
2018-05-13 13:06:36 +02:00
Johnny Sorocil
e3575a86c5
Add "#ifdef __FreeBSD__"
2018-05-05 13:02:44 +02:00
Clifford Wolf
5c03aeac60
Add "yosys -e regex" for turning warnings into errors
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-04 15:27:28 +02:00
Clifford Wolf
0acea3548b
Set stack size to at least 128 MB (large stack needed for parsing huge expressions)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-27 15:04:10 +02:00
Edmond Cote
64ea55056a
Rename rename to renames
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Create TCL alias for rename command. Using renames. Following the same convention as proc -> procs.
2018-03-20 15:50:50 -07:00
Larry Doolittle
82fecc98c0
Harmonize uses of _WIN32 macro
2018-03-11 16:01:30 +01:00
Clifford Wolf
e5534a080e
Improve handling of warning messages
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 22:35:59 +01:00
Clifford Wolf
2935e8ea41
Update copyright header
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 21:31:10 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
82c436587c
Do not create deep backtraces unless in ENABLE_DEBUG mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-03 15:04:39 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
c80315cea4
Bugfix in hierarchy handling of blackbox module ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-05 13:28:45 +01:00
Clifford Wolf
76afff7ef6
Add RTLIL::Const::is_fully_ones()
2017-12-14 02:06:39 +01:00
Clifford Wolf
96ad688849
Add SigSpec::is_fully_ones()
2017-12-14 01:29:09 +01:00
Kevin Kiningham
7350f7692a
Use quote includes for yosys.h
2017-12-13 13:27:52 -08:00
Clifford Wolf
9ae25039fb
Add support for editline as replacement for readline
2017-11-08 02:55:00 +01:00
Clifford Wolf
13eb47c692
Add src arguments to all cell creator helper functions
2017-09-09 10:16:48 +02:00
Clifford Wolf
8a66bd30c6
Update more stuff to use get_src_attribute() and set_src_attribute()
2017-09-01 12:26:55 +02:00
Jason Lowdermilk
71d43cfc08
Merge remote-tracking branch 'upstream/master'
2017-08-30 11:47:06 -06:00
Jason Lowdermilk
271e8ba7cd
fix indent level
2017-08-30 11:46:41 -06:00
Clifford Wolf
8530333439
Add {get,set}_src_attribute() methods on RTLIL::AttrObject
2017-08-30 11:39:11 +02:00
Jason Lowdermilk
32c0f1193e
Add support for source line tracking through synthesis phase
2017-08-29 14:46:35 -06:00
Clifford Wolf
d3b3dd8e88
Add hashlib support for hashing of pools
2017-08-22 13:04:33 +02:00
Clifford Wolf
bce0bb6e43
Add consteval support for $_ANDNOT_ and $_ORNOT_
2017-08-22 13:04:05 +02:00
Clifford Wolf
4ba5bd12c6
Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()
2017-08-18 11:40:08 +02:00
Clifford Wolf
159701962a
Auto-detect JSON front-end
2017-08-09 13:28:52 +02:00
Clifford Wolf
2336d5508b
Add log_warning_noprefix() API, Use for Verific warnings and errors
2017-07-27 12:17:04 +02:00
Clifford Wolf
493fedbaf9
Add "using std::get" to yosys.h
2017-07-25 14:52:34 +02:00
Clifford Wolf
c251e3a576
Change intptr_t to uintptr_t in hashlib.h
2017-07-18 17:38:19 +02:00
Robert Ou
f0741698fa
Fix build warnings for win64
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Win64 has a 32-bit long. Use intptr_t to work on any data model.
2017-07-17 12:36:43 -07:00
Clifford Wolf
1f517d2b96
Fix history namespace collision
2017-06-20 05:26:12 +02:00
Clifford Wolf
c0ca99483c
Store command history when terminating with an error
2017-06-20 04:41:58 +02:00
Clifford Wolf
05df3dbee4
Add "setundef -anyseq"
2017-05-28 11:59:05 +02:00
Clifford Wolf
662a047815
Enable readline and tcl in mxe builds
2017-05-17 20:46:22 +02:00
Clifford Wolf
6934b862d3
Add missing AndnotGate() and OrnotGate() declarations to rtlil.h
2017-05-17 19:10:57 +02:00
Clifford Wolf
05cdd58c8d
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
Clifford Wolf
fcb274a564
Add ConstEval defaultval feature
2017-04-05 11:25:22 +02:00
Clifford Wolf
b8d7f57f61
Add front-end detection for *.tcl files
2017-03-28 12:13:58 +02:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
c6d8d70109
Fix mingw compile issue (2nd attempt)
2017-02-23 14:21:02 +01:00
Clifford Wolf
0822b21844
Fix mingw compile issue (maybe.. I can't test it)
2017-02-23 13:59:02 +01:00
Clifford Wolf
e6d56d23b5
Fix eval implementation of $_NOR_
2017-02-16 12:17:03 +01:00
Clifford Wolf
828303791b
Add "yosys -w" for suppressing warnings
2017-02-12 11:11:00 +01:00
Clifford Wolf
63dfdb5d7f
Add log_wire() API
2017-02-11 11:08:36 +01:00
Clifford Wolf
aab58045a8
Fix undef propagation bug in $pmux SAT model
2017-02-05 22:43:33 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
b54972c112
Fix RTLIL::Memory::start_offset initialization
2017-01-25 17:00:59 +01:00