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3995 Commits

Author SHA1 Message Date
Andrew Zonenberg db20e3f1c2 Fixed undeclared "count" in GP_COUNT14_ADV 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 3618ca2218 Fixed typo in last commit 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 4da1a327c0 Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else. 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 4504dd78e9 Fixed typo in COUNT8 model 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 60dd5dba7b Moved GP_POR out of digital cells b/c it has delays 2017-08-14 10:45:39 -07:00
Andrew Zonenberg f55d4cc2fd Improved cells_sim_digital model for GP_COUNT8 2017-08-14 10:45:39 -07:00
Andrew Zonenberg fe3a932cfa Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 1bb150c231 Improved handling of constant connections in opt_rmports 2017-08-14 10:28:19 -07:00
Andrew Zonenberg 2877d5e504 Fixed handling of cell ports that aren't wires 2017-08-14 10:28:16 -07:00
Andrew Zonenberg 3dd7f42e2b opt_rmports: Fixed incorrect handling of multi-bit nets 2017-08-14 10:28:11 -07:00
Andrew Zonenberg 66aac06eee Removed commented out debug code 2017-08-14 10:28:04 -07:00
Andrew Zonenberg cca3cb5fbb Added opt_rmports pass (remove unconnected ports from top-level modules) 2017-08-14 10:27:59 -07:00
Clifford Wolf 007f29b9c2 Add support for set-reset cell variants to opt_rmdff 2017-08-09 13:29:52 +02:00
Clifford Wolf 159701962a Auto-detect JSON front-end 2017-08-09 13:28:52 +02:00
Clifford Wolf c4a7958f70 Add handling of constant reset signals to opt_rmdff 2017-08-06 13:27:18 +02:00
Clifford Wolf 48b2b376d0 Add "yosys-smtbmc --smtc-init --smtc-top --noinit" 2017-08-04 17:09:08 +02:00
Clifford Wolf 1dc921d9a1 Add "-undefined dynamic_lookup" to OSX "yosys-config --ldflags" 2017-08-04 11:24:58 +02:00
Clifford Wolf 5c09f24e48 Fix typo in "abc" pass help message 2017-07-29 16:21:58 +02:00
Clifford Wolf 15073790bf Add merging of "past FFs" to verific importer 2017-07-29 00:10:38 +02:00
Clifford Wolf e7d1277a2c Add consolidation of init attributes to opt_clean, some opt_clean log fixes 2017-07-29 00:10:33 +02:00
Clifford Wolf d4b9602cbd Add minimal support for PSL in VHDL via Verific 2017-07-28 17:39:49 +02:00
Clifford Wolf 4cf890dac1 Add simple VHDL+PSL example 2017-07-28 17:39:43 +02:00
Clifford Wolf 5a828fff34 Improve Verific HDL language options 2017-07-28 15:32:54 +02:00
Clifford Wolf acd6cfaf67 Fix handling of non-user-declared Verific netbus 2017-07-28 11:31:27 +02:00
Clifford Wolf c1cfca8f54 Improve Verific SVA importer 2017-07-27 14:05:09 +02:00
Clifford Wolf 877ff1f75e Add counter.sv SVA test 2017-07-27 12:37:16 +02:00
Clifford Wolf 2336d5508b Add log_warning_noprefix() API, Use for Verific warnings and errors 2017-07-27 12:17:04 +02:00
Clifford Wolf d9641621d9 Add "verific -import -n" and "verific -import -nosva" 2017-07-27 11:54:45 +02:00
Clifford Wolf b24f737759 Improve SVA tests, add Makefile and scripts 2017-07-27 11:42:05 +02:00
Clifford Wolf 90d8329f64 Improve Verific SVA import: negedge and $past 2017-07-27 11:40:07 +02:00
Clifford Wolf 147ff96ba3 Improve Verific SVA importer 2017-07-27 10:39:39 +02:00
Clifford Wolf 649bb9374f Add "opt_expr -fine" feature to remove neutral bits from reduce and logic operators 2017-07-26 18:28:55 +02:00
Clifford Wolf 530040ba6f Improve Verific bindings (mostly related to SVA) 2017-07-26 18:00:01 +02:00
Clifford Wolf abd3b4e8e7 Improve "help verific" message 2017-07-25 15:13:22 +02:00
Clifford Wolf 6dbe1d4c92 Add "verific -extnets" 2017-07-25 14:53:11 +02:00
Clifford Wolf 493fedbaf9 Add "using std::get" to yosys.h 2017-07-25 14:52:34 +02:00
Clifford Wolf c97c92e4ec Improve "verific -all" handling 2017-07-25 13:33:25 +02:00
Clifford Wolf 41be530c4e Add "verific -import -d <dump_file" 2017-07-24 13:57:16 +02:00
Clifford Wolf 92d3aad670 Add "verific -import -flatten" and "verific -import -v" 2017-07-24 11:29:06 +02:00
Clifford Wolf 84f15260b5 Add more SVA test cases for future Verific work 2017-07-22 16:35:46 +02:00
Clifford Wolf 5be535517c Add "verific -import -k" 2017-07-22 16:16:44 +02:00
Clifford Wolf b6bd12fade Add error for cell output ports that are connected to constants 2017-07-22 15:08:30 +02:00
Clifford Wolf 024ba310ec Add some simple SVA test cases for future Verific work 2017-07-22 12:31:08 +02:00
Clifford Wolf 2785aaffeb Improve docs for verific bindings, add simply sby example 2017-07-22 11:58:51 +02:00
Clifford Wolf b3bc7068d1 Fix handling of empty cell port assignments (i.e. ignore them) 2017-07-21 19:32:31 +02:00
Clifford Wolf 36cf18ac4c Fix "read_blif -wideports" handling of cells with wide ports 2017-07-21 16:21:12 +02:00
Clifford Wolf 26766da343 Add a paragraph about pre-defined macros to read_verilog help message 2017-07-21 14:34:53 +02:00
Clifford Wolf 3a8f6f0f51 Add verilator support to testbenches generated by yosys-smtbmc 2017-07-21 14:33:29 +02:00
Clifford Wolf c251e3a576 Change intptr_t to uintptr_t in hashlib.h 2017-07-18 17:38:19 +02:00
Clifford Wolf dbb2f755c1 Merge pull request #363 from rqou/master 
Miscellaneous build tweaks
 2017-07-18 15:21:12 +02:00