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11685 Commits

Author SHA1 Message Date
github-actions[bot] 207417617d Bump version 2022-03-26 00:13:30 +00:00
NotAFile 349c0ff0a7 Add some more reserve calls to RTLIL::Const 
This results in a slight ~0.22% total speedup synthesizing vexriscv
 2022-03-25 18:38:00 +00:00
Miodrag Milanović a7e7a9f485
Merge pull request #3249 from YosysHQ/micko/no_startoffset 
Add -no-startoffset option to write_aiger
 2022-03-25 14:29:21 +01:00
Miodrag Milanovic 245ecb0529 Import verific netlist in consistent order 2022-03-25 13:44:16 +01:00
Miodrag Milanovic 4fd8b38d7a Add -no-startoffset option to write_aiger 2022-03-25 08:44:45 +01:00
github-actions[bot] afe258e6f8 Bump version 2022-03-25 00:13:36 +00:00
Miodrag Milanović 89dcd7c31e
Merge pull request #3243 from nakengelhardt/fix_aiw_comment 
smtbmc: ignore # comment lines
 2022-03-24 17:25:09 +01:00
Jannis Harder 5e4d804e53 yosys-smtbmc: Option to keep going after failed assertions in BMC mode 2022-03-24 16:01:14 +01:00
Jannis Harder e43ebf8527 yosys-smtbmc: Fix typo in help text, remove trailing whitespace 2022-03-24 16:01:14 +01:00
gatecat 8b64dc1dce abc9_ops: Also derive blackboxes with timing info 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-24 14:36:07 +00:00
N. Engelhardt a7ee01065a ignore # comment lines 2022-03-24 10:19:17 +01:00
github-actions[bot] 6318db6152 Bump version 2022-03-23 00:14:55 +00:00
Miodrag Milanovic 15c7205908 Update abc with latest fix 2022-03-22 18:47:48 +01:00
Miodrag Milanovic 322ab1cd54 Proper SigBit forming in sim 2022-03-22 14:43:18 +01:00
Miodrag Milanovic ff3b0c2c46 Proper SigBit forming in sim 2022-03-22 14:22:32 +01:00
github-actions[bot] f45b290820 Bump version 2022-03-22 00:15:19 +00:00
Marcelina Kościelnicka be9595e18f xilinx: Add RAMB4* blackboxes 2022-03-21 13:11:52 +01:00
github-actions[bot] 3bf1070245 Bump version 2022-03-19 00:12:57 +00:00
Miodrag Milanovic 55eed8df57 More verbose warnings 2022-03-18 14:47:35 +01:00
Miodrag Milanović 0c5279b73d
Merge pull request #3236 from YosysHQ/micko/tb_initial 
Recognize registers and set initial state for them in tb
 2022-03-17 17:15:36 +01:00
github-actions[bot] e1d4863a19 Bump version 2022-03-17 00:13:12 +00:00
Miodrag Milanovic 1f3423cd7d Recognize registers and set initial state for them in tb 2022-03-16 14:35:39 +01:00
Miodrag Milanovic e217e3017a Update sim help message. 2022-03-16 07:55:57 +01:00
github-actions[bot] 66914b6eb3 Bump version 2022-03-15 01:09:43 +00:00
YRabbit 19b7633aca gowin: add support for Double Data Rate primitives 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-03-14 23:14:21 +01:00
Miodrag Milanović 25d6fdfea7
Merge pull request #3232 from YosysHQ/micko/fst2tb 
Added fst2tb pass for generating testbench
 2022-03-14 20:01:55 +01:00
Miodrag Milanovic f5c20b8286 Added fst2tb pass for generating testbench 2022-03-14 19:06:29 +01:00
Claire Xen 5e2992dae2
Merge pull request #3213 from antonblanchard/abc-typo 
abc: Fix {I} and {P} substitution
 2022-03-14 16:05:23 +01:00
Miodrag Milanovic 27c5bafc95 Proper example code 2022-03-14 15:39:11 +01:00
github-actions[bot] a502570c25 Bump version 2022-03-12 01:02:32 +00:00
Miodrag Milanović cbece4af0c
Merge pull request #3229 from YosysHQ/micko/sim_date 
Add date parameter to enable full date/time and version info
 2022-03-11 19:02:57 +01:00
Miodrag Milanović 532343dcfa
Merge pull request #3222 from zachjs/prune-linux-ci 
Prune Linux CI builds
 2022-03-11 19:02:37 +01:00
Miodrag Milanović 04de9bb655
Merge pull request #3228 from YosysHQ/micko/disable_tests 
Disable tests on most of platforms
 2022-03-11 19:02:19 +01:00
Claire Xenia Wolf e21badd4b3 Add "sim -q" option 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-03-11 16:26:11 +01:00
Miodrag Milanovic 37de369ba7 Add date parameter to enable full date/time and version info 2022-03-11 16:01:59 +01:00
Claire Xenia Wolf be32de1caa Small fix in "sim" help message 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-03-11 15:36:23 +01:00
Miodrag Milanović 2f44683f4f
Merge pull request #3226 from YosysHQ/micko/btor2witness 
Sim support for btor2 witness files
 2022-03-11 15:29:34 +01:00
Miodrag Milanovic 5204694123 FstData already do conversion to VCD 2022-03-11 15:21:36 +01:00
Miodrag Milanovic b72c779204 Support cell name in btor witness file 2022-03-11 15:11:14 +01:00
Claire Xenia Wolf d340f302f6 Fix handling of some formal cells in btor back-end 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-03-11 14:21:12 +01:00
Miodrag Milanovic ebe2ee431e handle state names of $anyconst and $anyseq 2022-03-11 14:04:02 +01:00
Zachary Snow 5e7ea57d8e Prune Linux CI builds 2022-03-11 12:07:48 +01:00
Miodrag Milanovic 357336339a Proper write of memory data 2022-03-11 11:19:53 +01:00
Miodrag Milanovic 75c0391f06 Disable tests on most of platforms 2022-03-10 11:05:00 +01:00
github-actions[bot] eb8c61f033 Bump version 2022-03-10 01:11:52 +00:00
Lofty 9f7a55c99f intel_alm: M10K write-enable is negative-true 2022-03-09 20:18:06 +00:00
Miodrag Milanovic 295b0d1899 Start work on memory init 2022-03-09 18:34:02 +01:00
Miodrag Milanovic f37ac5d934 Fixes and error check 2022-03-09 09:48:29 +01:00
Miodrag Milanovic ede348cdc2 cleanup 2022-03-07 16:32:32 +01:00
Miodrag Milanovic 1b1ecd4ab0 Error checks for aiger witness 2022-03-07 15:00:14 +01:00