riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

gowin: add support for Double Data Rate primitives 

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit 2022-03-15 07:41:30 +10:00 committed by Marcelina Kościelnicka
parent 25d6fdfea7
commit 19b7633aca
1 changed files with 25 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
techlibs/gowin/cells_sim.v
View File

@ -590,6 +590,31 @@ module TLVDS_OBUF (I, O, OB);
assign OB = ~I;
endmodule
(* blackbox *)
module ODDR(D0, D1, TX, CLK, Q0, Q1);
input D0;
input D1;
input TX;
input CLK;
output Q0;
output Q1;
parameter TXCLK_POL = 0;
parameter INIT = 0;
endmodule
(* blackbox *)
module ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);
input D0;
input D1;
input CLEAR;
input TX;
input CLK;
output Q0;
output Q1;
parameter TXCLK_POL = 0;
parameter INIT = 0;
endmodule
module GSR (input GSRI);
wire GSRO = GSRI;
endmodule