mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3226 from YosysHQ/micko/btor2witness
Sim support for btor2 witness files
This commit is contained in:
Miodrag Milanović
GitHub
commit
2f44683f4f
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@ -678,7 +678,7 @@ struct BtorWorker
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int sid = get_bv_sid(GetSize(sig_y));
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int nid = next_nid++;
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btorf("%d state %d\n", nid, sid);
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btorf("%d state %d%s\n", nid, sid, getinfo(cell).c_str());
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if (cell->type == ID($anyconst)) {
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int nid2 = next_nid++;
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@ -699,7 +699,7 @@ struct BtorWorker
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int one_nid = get_sig_nid(State::S1);
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int zero_nid = get_sig_nid(State::S0);
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initstate_nid = next_nid++;
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btorf("%d state %d\n", initstate_nid, sid);
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btorf("%d state %d%s\n", initstate_nid, sid, getinfo(cell).c_str());
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btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid);
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btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid);
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}
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@ -326,6 +326,16 @@ struct SimInstance
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return did_something;
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}
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void set_memory_state(IdString memid, Const addr, Const data)
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{
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auto &state = mem_database[memid];
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int offset = (addr.as_int() - state.mem->start_offset) * state.mem->width;
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for (int i = 0; i < GetSize(data); i++)
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if (0 <= i+offset && i+offset < GetSize(data))
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state.data.bits[i+offset] = data.bits[i];
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}
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void update_cell(Cell *cell)
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{
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if (ff_database.count(cell))
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@ -961,7 +971,7 @@ struct SimWorker : SimShared
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}
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}
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void run_cosim(Module *topmod, int numcycles)
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void run_cosim_fst(Module *topmod, int numcycles)
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{
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log_assert(top == nullptr);
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fst = new FstData(sim_filename);
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@ -1092,13 +1102,17 @@ struct SimWorker : SimShared
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delete fst;
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}
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void run_cosim_witness(Module *topmod)
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void run_cosim_aiger_witness(Module *topmod)
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{
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log_assert(top == nullptr);
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if ((clock.size()+clockn.size())==0)
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log_error("Clock signal must be specified.\n");
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std::ifstream mf(map_filename);
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std::string type, symbol;
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int variable, index;
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dict<int, std::pair<SigBit,bool>> inputs, inits, latches;
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if (mf.fail())
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log_cmd_error("Not able to read AIGER witness map file.\n");
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while (mf >> type >> variable >> index >> symbol) {
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RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
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Wire *w = topmod->wire(escaped_s);
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@ -1183,6 +1197,131 @@ struct SimWorker : SimShared
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register_output_step(10*cycle);
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write_output_files();
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}
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std::vector<std::string> split(std::string text, const char *delim)
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{
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std::vector<std::string> list;
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char *p = strdup(text.c_str());
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char *t = strtok(p, delim);
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while (t != NULL) {
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list.push_back(t);
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t = strtok(NULL, delim);
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}
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free(p);
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return list;
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}
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std::string signal_name(std::string const & name)
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{
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size_t pos = name.find_first_of("@");
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if (pos==std::string::npos) {
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pos = name.find_first_of("#");
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if (pos==std::string::npos)
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log_error("Line does not contain proper signal name `%s`\n", name.c_str());
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}
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return name.substr(0, pos);
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}
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void run_cosim_btor2_witness(Module *topmod)
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{
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log_assert(top == nullptr);
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if ((clock.size()+clockn.size())==0)
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log_error("Clock signal must be specified.\n");
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std::ifstream f;
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f.open(sim_filename.c_str());
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if (f.fail() || GetSize(sim_filename) == 0)
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log_error("Can not open file `%s`\n", sim_filename.c_str());
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int state = 0;
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int cycle = 0;
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top = new SimInstance(this, scope, topmod);
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register_signals();
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int prev_cycle = 0;
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int curr_cycle = 0;
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std::vector<std::string> parts;
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size_t len = 0;
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while (!f.eof())
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{
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std::string line;
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std::getline(f, line);
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if (line.size()==0) continue;
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if (line[0]=='#' || line[0]=='@' || line[0]=='.') {
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if (line[0]!='.')
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curr_cycle = atoi(line.c_str()+1);
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else
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curr_cycle = -1; // force detect change
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if (curr_cycle != prev_cycle) {
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log("Simulating cycle %d.\n", cycle);
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set_inports(clock, State::S1);
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set_inports(clockn, State::S0);
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update();
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register_output_step(10*cycle+0);
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set_inports(clock, State::S0);
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set_inports(clockn, State::S1);
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update();
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register_output_step(10*cycle+5);
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cycle++;
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prev_cycle = curr_cycle;
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}
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if (line[0]=='.') break;
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continue;
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}
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switch(state)
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{
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case 0:
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if (line=="sat")
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state = 1;
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break;
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case 1:
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if (line[0]=='b' || line[0]=='j')
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state = 2;
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else
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log_error("Line does not contain property.\n");
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break;
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default: // set state or inputs
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parts = split(line, " ");
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len = parts.size();
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if (len<3 || len>4)
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log_error("Invalid set state line content.\n");
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RTLIL::IdString escaped_s = RTLIL::escape_id(signal_name(parts[len-1]));
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if (len==3) {
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Wire *w = topmod->wire(escaped_s);
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if (!w) {
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Cell *c = topmod->cell(escaped_s);
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if (!c)
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log_warning("Wire/cell %s not present in module %s\n",log_id(escaped_s),log_id(topmod));
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else if (c->type.in(ID($anyconst), ID($anyseq))) {
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SigSpec sig_y= c->getPort(ID::Y);
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if ((int)parts[1].size() != GetSize(sig_y))
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log_error("Size of wire %s is different than provided data.\n", log_signal(sig_y));
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top->set_state(sig_y, Const::from_string(parts[1]));
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}
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} else {
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if ((int)parts[1].size() != w->width)
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log_error("Size of wire %s is different than provided data.\n", log_signal(w));
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top->set_state(w, Const::from_string(parts[1]));
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}
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} else {
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Cell *c = topmod->cell(escaped_s);
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if (!c)
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log_error("Cell %s not present in module %s\n",log_id(escaped_s),log_id(topmod));
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if (!c->is_mem_cell())
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log_error("Cell %s is not memory cell in module %s\n",log_id(escaped_s),log_id(topmod));
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Const addr = Const::from_string(parts[1].substr(1,parts[1].size()-2));
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Const data = Const::from_string(parts[2]);
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top->set_memory_state(c->parameters.at(ID::MEMID).decode_string(), addr, data);
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}
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break;
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}
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}
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register_output_step(10*cycle);
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write_output_files();
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}
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};
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struct VCDWriter : public OutputWriter
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@ -1311,14 +1450,19 @@ struct AIWWriter : public OutputWriter
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void write(std::map<int, bool> &) override
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{
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if (!aiwfile.is_open()) return;
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if (worker->map_filename.empty())
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log_cmd_error("For AIGER witness file map parameter is mandatory.\n");
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std::ifstream mf(worker->map_filename);
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std::string type, symbol;
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int variable, index;
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if (mf.fail())
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log_cmd_error("Not able to read AIGER witness map file.\n");
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while (mf >> type >> variable >> index >> symbol) {
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RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
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Wire *w = worker->top->module->wire(escaped_s);
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if (!w)
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log_error("Wire %s not present in module %s\n",log_signal(w),log_id(worker->top->module));
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log_error("Wire %s not present in module %s\n",log_id(escaped_s),log_id(worker->top->module));
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if (index < w->start_offset || index > w->start_offset + w->width)
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log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
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if (type == "input") {
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@ -1483,6 +1627,13 @@ struct SimPass : public Pass {
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log(" enable debug output\n");
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log("\n");
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}
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static std::string file_base_name(std::string const & path)
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{
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return path.substr(path.find_last_of("/\\") + 1);
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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SimWorker worker;
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@ -1632,11 +1783,21 @@ struct SimPass : public Pass {
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if (worker.sim_filename.empty())
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worker.run(top_mod, numcycles);
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else
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if (worker.map_filename.empty())
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worker.run_cosim(top_mod, numcycles);
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else
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worker.run_cosim_witness(top_mod);
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else {
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std::string filename_trim = file_base_name(worker.sim_filename);
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if (filename_trim.size() > 4 && ((filename_trim.compare(filename_trim.size()-4, std::string::npos, ".fst") == 0) ||
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filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vcd") == 0)) {
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worker.run_cosim_fst(top_mod, numcycles);
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} else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".aiw") == 0) {
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if (worker.map_filename.empty())
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log_cmd_error("For AIGER witness file map parameter is mandatory.\n");
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worker.run_cosim_aiger_witness(top_mod);
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} else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".wit") == 0) {
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worker.run_cosim_btor2_witness(top_mod);
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} else {
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log_cmd_error("Unhandled extension for simulation input file `%s`.\n", worker.sim_filename.c_str());
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}
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}
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}
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} SimPass;
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