Marcelina Kościelnicka
71dfbf33b2
Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.
2022-06-02 23:16:12 +02:00
Marcelina Kościelnicka
a04b025abf
ecp5: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
e14302a3ea
ecp5: Add support for mapping aldff.
2021-10-27 16:18:05 +02:00
Eddie Hung
f03e2c30aa
abc9: replace cell type/parameters if derived type already processed ( #2991 )
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* Add close bracket
* Add testcase
* Replace cell type/param if in unmap_design
* Improve abc9_box error message too
* Update comment as per review
2021-09-09 10:05:55 -07:00
Claire Xenia Wolf
0ada13cbe2
Use HTTPS for website links, gatecat email
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git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g ;
2021-06-09 12:16:56 +02:00
Claire Xenia Wolf
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
gatecat
cae905f551
Blackbox all whiteboxes after synthesis
...
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
Marcelina Kościelnicka
9a4f420b4b
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka
372521ca56
ecp5: Use dfflegalize.
2020-07-05 18:49:41 +02:00
Marcelina Kościelnicka
88e7f90663
Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Eddie Hung
76e0cc8276
ecp5: cleanup unused +/ecp5/abc9_model.v
2020-05-23 08:17:40 -07:00
Eddie Hung
cea614f5ae
ecp5: latches_map.v if *not* -asyncprld
2020-05-14 10:33:57 -07:00
Eddie Hung
fdc340db8e
ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v
2020-05-14 10:33:57 -07:00
Eddie Hung
39759d5f0e
ecp5: fix rebase mistake
2020-05-14 10:33:57 -07:00
Eddie Hung
6c34945371
xilinx/ice40/ecp5: zinit requires selected wires, so select them all
2020-05-14 10:33:56 -07:00
Eddie Hung
7cd3f4a79b
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
2020-05-14 10:33:56 -07:00
Eddie Hung
8fbb55f4ab
synth_*: no need to explicitly read +/abc9_model.v
2020-05-14 10:33:56 -07:00
Eddie Hung
0d84ff3fc4
Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"
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This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b.
2020-05-14 10:33:56 -07:00
Eddie Hung
34c7732642
ecp5: add synth_ecp5 -dff to work with -abc9
2020-05-14 10:33:56 -07:00
Eddie Hung
5d5029fa75
ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init
2020-05-14 10:33:56 -07:00
Eddie Hung
e6b55e8b38
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
2020-05-04 11:44:00 -07:00
Marcelina Kościelnicka
38a0c30d65
Get rid of dffsr2dff.
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This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part. Thus, it never
actually does anything and can be safely removed.
2020-04-15 16:22:37 +02:00
whitequark
93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style
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ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
2020-04-10 14:51:01 +00:00
whitequark
763401fc82
ecp5: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
Eddie Hung
a85c55113f
synth_ecp5: use +/abc9_model.v
2020-02-27 10:17:29 -08:00
Eddie Hung
46a89d7264
ecp5: deprecate abc9_{arrival,required} and *.{lut,box}
2020-02-27 10:17:29 -08:00
Eddie Hung
0b0148399c
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. ( #1673 )
2020-02-03 14:57:17 +01:00
Eddie Hung
53aa51dc92
Re-enable &mfs for synth_{ecp5,xilinx}
2020-01-06 16:21:04 -08:00
whitequark
f8d5920a7e
Merge pull request #1604 from whitequark/unify-ram-naming
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Harmonize BRAM/LUTRAM descriptions across all of Yosys
2020-01-02 21:06:17 +00:00
whitequark
550310e264
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
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This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 12:30:00 +00:00
Eddie Hung
79448f9be0
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
Eddie Hung
aa6d06c1b5
Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
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This reverts commit 6008bb7002
.
2019-12-30 13:28:29 -08:00
Eddie Hung
71906fab51
Nitpick cleanup for ecp5
2019-12-27 16:57:08 -08:00
Eddie Hung
10e82e103f
Revert "Optimise write_xaiger"
2019-12-20 12:05:45 -08:00
Eddie Hung
df626ee7ab
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
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Optimise write_xaiger
2019-12-19 12:24:03 -05:00
David Shah
184c0e796a
ecp5: Add support for mapping PRLD FFs
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Signed-off-by: David Shah <dave@ds0.me>
2019-12-07 13:04:36 +00:00
Eddie Hung
98c9ea605b
techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
2019-12-06 17:05:02 -08:00
David Shah
51e4e29bb1
ecp5: Use new autoname pass for better cell/net names
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-15 21:03:11 +00:00
David Shah
fa989e59e5
ecp5: Pass -nomfs to abc9
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Fixes #1459
Signed-off-by: David Shah <dave@ds0.me>
2019-10-20 10:30:41 +01:00
David Shah
7b1a6706d8
ecp5: Add attrmvcp to copy syn_useioff to driving FF
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-10 15:58:31 +01:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
9fef1df3c1
Panic over. Model was elsewhere. Re-arrange for consistency
2019-10-04 10:48:44 -07:00
Eddie Hung
84825f9378
Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once
2019-09-26 10:45:14 -07:00
Eddie Hung
e742478e1d
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-05 13:01:27 -07:00
David Shah
6919c0f9b0
Merge branch 'master' into xc7dsp
2019-08-30 13:57:15 +01:00
Eddie Hung
8d820a9884
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-28 15:19:10 -07:00
David Shah
fc001b4731
ecp5: Add GSR support
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-27 13:07:06 +01:00
Eddie Hung
d46dc9c5b4
ecp5 to use -max_iter 1
2019-08-20 19:18:36 -07:00